Looking for the latest version? Download jMIPS-2.0c.zip (1.4 MB)
Name Modified Size Downloads / Week Status
patch 2012-03-04 0
jMIPS-2.0c.zip 2013-03-27 1.4 MB 0
jMIPS-2.0c.tgz 2013-03-27 1.4 MB 0
README 2013-03-27 4.0 kB 0
jMIPS-2.0b.zip 2013-03-26 1.6 MB 0
jMIPS-2.0b.tgz 2013-03-26 1.5 MB 0
jMIPS-2.0a.zip 2013-03-23 1.4 MB 0
jMIPS-2.0a.tgz 2013-03-23 1.4 MB 0
jMIPS-1.7e.tgz 2012-04-02 456.6 kB 0
jMIPS-1.7e.zip 2012-04-02 489.1 kB 0
jMIPS-1.8a.zip 2012-04-01 1.6 MB 0
jMIPS-1.8a.tgz 2012-04-01 1.5 MB 0
jMIPS-1.7d.tgz 2012-03-09 449.8 kB 0
jMIPS-1.7d.zip 2012-03-09 479.7 kB 0
jmips-1.7c.zip 2012-02-23 495.4 kB 0
jmips-1.7c.tgz 2012-02-23 405.4 kB 0
jMIPS-1.8.tgz 2011-03-29 317.5 kB 0
jMIPS-1.8.zip 2011-03-29 350.5 kB 0
jMIPS-1.7b.zip 2011-01-11 349.1 kB 0
jMIPS-1.7b.tgz 2011-01-11 315.7 kB 0
jMIPS-1.7a.tgz 2011-01-10 206.3 kB 0
jMIPS-1.7a.zip 2011-01-10 241.7 kB 0
jMIPS-1.7.zip 2011-01-02 349.4 kB 0
jMIPS-1.7.tgz 2011-01-02 315.8 kB 0
jMIPS-1.6.zip 2010-12-23 332.8 kB 0
jMIPS-1.6.tgz 2010-12-23 300.8 kB 0
jMIPS-1.5.zip 2010-12-22 328.7 kB 0
jMIPS-1.5.tgz 2010-12-22 296.1 kB 0
jMIPS-1.4.zip 2010-12-11 329.0 kB 0
jMIPS-1.4.tgz 2010-12-11 296.6 kB 0
jMIPS-1.3.zip 2010-12-08 336.5 kB 0
jMIPS-1.3.tgz 2010-12-08 304.4 kB 0
jMIPS-1.2.zip 2010-11-26 522.0 kB 0
jMIPS-1.2.tgz 2010-11-26 476.1 kB 0
jMIPS-1.1.zip 2010-05-30 698.0 kB 0
jMIPS-1.1.tgz 2010-05-30 652.1 kB 0
jMIPS-1.0.zip 2010-05-23 689.8 kB 0
jMIPS-1.0.tgz 2010-05-23 643.1 kB 0
Totals: 38 Items   23.2 MB
2.0c Deal with unimplemented functions by running handler. Re-simplify Register interface .. just read/write. Remove IBUS/OVF internals in favour of conf.ovf etc. 2.0b 64-bit corrections and do ALU via decomposition to 32, 16 and 8 bit units. 2.0a Trial port of 64-bit version from 1.3b. 1.8a Add CPU6 and CPU7. Documentation updated from Wiki throughout. 1.8 Correct branch delay-slot handling, in which the instr after a jump or branch is always executed. Switched on with CPU_BRANCH_DELAY_SLOT=1. Irqs immediately following a delay slot needed to know the orig branch or jump destination in order to set EPC correctly, so implemented that. 1.7b Complete cycle of known bug-fixes. Fix ORI, XORI, ANDI bug (16 bit immediate val should be zero-extended always, not sign-extended). Remove obscure lock cycle between Screen (print), Keyboard (read) and CPU. Even some corrections in ALU, which now gets an overflow flag. 1.7a Retract half-baked MIPS delay-slot implementation to make sure timing stays stable - and code too. So 1.7a just contains the bug fixes from 1.7 over 1.6. 1.7 Add treatment of LT to ALU. Fix JALR bug in CPU2-5. Increase IOBus speed to 66MHz to help optimization of hello_world. Increase Console buffer to 4096 to allow CPU1-4 to output more than 128 chars on the dhrystone benchmark. Implement SRAV. FIx SLT and SLTU bug in ALU. Clear up some kind of DIV or MFLO -related bug that disappeared without me being able to be sure what it was. Will probably reappear. Notice that gcc seems to generate assembler for c=a/b that depends on the instr after a branch being executed. It produces bnez b, FOO div a,b break 7 FOO: mflo c It's a silly save of one instr. It could be bnez b, FOO nop div a,b break 7 b BAR FOO: div a,b mflo c BAR: My compile options are -O0 -static -DMIPS -mips1 -mabi=32 -msoft-float -mno-memcpy gcc version 4.3.5 (Debian 4.3.5-4). I've now arranged for this delay slot to be executed in CPU2-5. In CPU5 I've forbidden IRQ to interrupt a jump or branch, to avoid flushing the delay slot following. In CPU2-5 jump or branch don't flush the following instr in the pipeline. Don't know what to do in CPU1. I've also made ELF more sophisticated I hope. It loads sections individually. 1.6 Remove a bug in Register behaviour that was making life too easy. Registers should have shown a written value for read only on the next clock, but that did not always happen (simply: buggy code). That permitted instructions to be in the pipeline together that should never have been in there at the same time, as one wrote what the other wanted to read. However, a bug in the pipeline Read stage (off-by-one bug) allowed it, and no misbehaviour accrued because of the Register bug. From the outside, speeds were showing up as too high for the level of hardware optimization, since instructions could be - and were - crowded closer in the pipeline than they should have been. 1.5 Remove more printfs so that older Javas can compile and run the code. Refine locking in CPU5 so that IRQ and IACK changes are locked and signalled through cpu, while the Clock (class) is reserved for signalling time-based events. That fixes a rare deadlock due (presumably) to somehow peripherals running code synchronized on the clock and vice-versa (without flagging every entry into a synchronized block I can't locate the problem, but it looks that way). 1.4 Provide 64-bit utility routines for possible cache use. Mend bug in CPU5 that tested for JALR wrongly in Irq stage and resulted in sporadic loop on SMP platforms doing return from RFE to addr 0. Remove printf references in favour of print, so that can run under kaffe (1.1.8, java 1.4) and jamvm (1.5.1, java 1.5) as well as under the openjdk JVM (1.6.0, java 1.6). 1.3 Cleanups 1.2 Cleanups 1.1 Registers flip on a clock edge only. Writes aren't readable until after next clock tick. 1.0
Source: README, updated 2013-03-27

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