DesignPlayer- Unified Solution for IP-XACT, IP Assembly and RTL
===============================================================
About
This is a unified and comprehensive solution for IP-XACT, IP Assembly
and miscellaneous utilities around VHDL and Verilog. See the example
directory to get an understanding of the tools and their usages. This tool
can be logically divided into following three different groups.
(1) Baya : Primarily aimed for the IP Assembly solution
(2) IP-XACT: Primarily aimed for the IP-XACT solution
(2) RTLUtils : Consolidates all the VHDL and Verilog utilities
See the Methodologies directory and the documents IP-XACT-Packaging.txt,
SoC-Integration.txt and README.txt in that directory to get an overview
of the design methodologies for SoC Integration and IP-XACT packaging.
License Setting
===============
Set the EDAUTILS_LICENSE_KEY environment variable before running the tool.
You may refer the page www.computerhope.com/issues/ch000549.htm to know howto set
environment variables in Windows.
Howto run this Tool ?
Source the setup_env file to set the environment variable EDAUTILS_ROOT
CLASSPATH and the the PATH variables properly.
Alternatively for Unix
setenv EDAUTILS_ROOT /usr/user1/DesignPlayer-linux.x86/01MAY2014 ( this instalation directory )
set path = ( $EDAUTILS_ROOT/bin $path )
And for Windows
set EDAUTILS_ROOT=D:\edautils\DesignPlayer-win32.x86_64\01MAY2014 ( this instalation directory )
set PATH="%path%;%EDAUTILS_ROOT%\bin"
Then go to the relevant example directory and execute the run file.
The run file should give an idea about howto run use the same for your need.
Go through the explanation in the DesinPlayer webgage on howto use this
tool. You can also watch the video clippings for the demo of this tool.
Do not hesitate to drop a mailto help@edautils.com for any assistance.
Tcl Commands
============
[1] Command : baya_get_current_module
Description: returns the currently active design.
[2] Command : baya_get_file
Description: returns the file name where the database needs to be saved
[3] Command : baya_get_line
Description: returns the line number to be saved for the construct(s)
to be created by the next set of Baya command(s)
[4] Command : baya_get_root
Description: returns the root of the design database
[5] Command : baya_set_current_design
Description: sets the specified module as the currently active module.
Options :
-name <module name> , mandatory option to specify the module name.
Example : baya_set_current_design -name foo
[6] Command : baya_set_current_module
Description: sets the specified module as the currently active module.
Options :
-name <module name> , mandatory option to specify the module name.
Example : baya_set_current_module -name foo
[7] Command : baya_set_file
Description: Sets the name of the file where the design database will be saved.
Options :
-name <file name> , mandatory option to specify the module name.
Example : baya_set_file -name foo.v
[8] Command : baya_set_line
Description: Sets the number for the objects to be created in the following commands.
This command is mostly useful to debug the in memory design database ...
Options :
-num <Line number> , mandatory option to specify the line number.
Example : baya_set_line -num 10
[9] Command : baya_add_timescale
Description: Adds `timescale directive in the generated RTL
Options :
-delay <reference> , mandatory input to specify the reference time value e.g. 1ns .
-precision <value> , mandatory input to specify the precison value e.g. 10ps .
Example : baya_add_timescale -delay 1ns -precision 10ps
[10] Command : baya_add_define_directive
Description: Adds `define directive in the generated RTL
Options :
-var <name> , mandatory input to specify the name of the identifier/variable to be defined
-value <value> , optional input to set value to the given macro
Example : baya_add_define_directive -var DATASIZE -value 16
[11] Command : baya_add_include_file
Description: Adds `include directive in the generated RTL
Options :
-name < file name> , mandatory input to specify the name of the file to be included
-module <module name> , optional input, name of the module where this file
is to be included. If not specified then the file will
get included in the current module.
-contains_params , optional boolean switch to specify that the specified file contains parameter declaration.
If this switch is specified then this file will get included just before the port declaration.
Example : baya_add_include_file -name top.h -contains_params
[12] Command : baya_add_import
Description: Associates import statement with the current module
Options :
-symbol < symbol > , mandatory input to specify the symbols to be imported. There should NOT be any space in the symbolname or star and package name
Example : baya_add_import -symbol mypack::mystruct
baya_add_import -symbol mypack::*
[13] Command : baya_exclude_auto_connections
Description: Excludes specified connections while making the automatic connections.
This command must be called before calling the command baya_auto_connect .
Options : -connections <port1,port2,port3(inst1:inst2)>, mandatory switch
to enlist the ports which should NOT be connected automatically
You can disable auto connection between any two instances by giving value
as A(inst1:inst2) where the A is the common port between the instances inst1 and inst2.
The port1, port2 are the top ports i.e. if you want
to disable auto connections of the top port1 and port2.
No space is allowed before and after the colon and the comma.
You can call this command multiple times with different
connection to avoid long line.
Example : baya_exclude_auto_connection -connections port1(inst1:inst2),port2(inst1,inst5)
[14] Command : baya_auto_connect
Description: Establishes automatic connection between all the ports/pins
of the given comma separated instances where the port/pin
names matches. No space is allowed before and after comma.
Options :
-insts <instance names> , mandatory option to specify the instances
between which the connection needs to be established.
The instance names must be separated with comma(,)
-exclude <port1,port2,port3(inst1:inst2)> , optional( use only if you need ) switch
to enlist the ports which should NOT be connected automatically
You can disable connection between any two instances by specifying
that as A(inst1:inst2) where it will NOT connect the inst1.A with inst2.A
where the A is the common port name and inst1 and inst2 are the instance names.
No space is allowed before and after the colon and the comma.
-align_msb , optional boolean switch to align the connections with MSB of the
bigger port(s) in case of port width mismatches.
Default is LSB aligned.
-pad < 0 or 1> , optional( use only if you need ) switch
to specify the the high/low value with which the
the extra bits of the mismatching input ports
needs to ve driven. Useful to handle port with mismatches.
-comment <"Inline comments to be printed"> , Provide comments in quotes
which will get printed next to this port mapping.
This option must be used as the last option of this command.
Example : baya_auto_connect -insts u_Inst1,u_Inst2
baya_auto_connect -insts u_Inst1,u_Inst2 -pad 1
baya_auto_connect -insts u_Inst1,u_Inst2,u_Inst3 -pad 0 -exclude portA,portB
baya_auto_connect -insts u_A,u_B,u_C,u_D -exclude portA,port_B(u_D:u_C),port_C(u_B:u_C)
baya_auto_connect -insts u_Inst1,u_Inst2,u_Inst3 -align_msb
[15] Command : baya_connect_interfaces
Description: Creates connection between two interfaces specified with -from and the -two switches.
Options :
-from <u_inst1.intf1>, mandatory option to specify the first interface often the one of type Master which drives.
-to <u_inst2.intf2>, mandatory option to specify the second interface often the one of type Slave which gets driven.
-intf_port_maps <formal1@actual1/formal2@actual2>, optional input for the port maps of the interface which will
connect the two instances' interfaces
-intf_param_maps <param1=value/param2=value>, optional input for the parameter maps for the interface which will
connect the two instances' interfaces
-exclude <port1:port2> , optional( use only if you need ) switch
to enlist the logical ports which should be ignored while connecting the interfaces
-align_msb , optional boolean switch to align the connections with MSB of the
bigger port(s) in case of port width mismatches.
Default is LSB aligned.
-pad < 0 or 1> , optional( use only if you need ) switch
to specify the the high/low value with which the
the extra bits of the mismatching input ports
needs to ve driven. Useful to handle port with mismatches.
-ifdef_var <macro name> , optional input, to specify the macro enclosing this interface map
-comment <"Inline comments to be printed"> , Provide comments in quotes which will
get printed next to this port mapping. This option must be used
as the last option of this command.
Example : baya_connect_interfaces -from u_Inst1.master_intf -to u_Inst2.slave_intf -intf_port_maps clk@gclk/reset@grst -intf_param_maps AWIDTH=64/DWIDTH=32
baya_connect_interfaces -from u_Inst1.master_intf -to u_Inst2.slave_intf -pad 1'b1
baya_connect_interfaces -from u_Inst1.master_intf -to u_Inst2.slave_intf -pad 1'b0 -exclude portA:portB
baya_connect_interfaces -from u_Inst1.master_intf -to u_Inst2.slave_intf -align_msb
[16] Command : baya_connect_ipxact_interfaces_by_converting_into_sv_interface
Description: Creates connection between two IP-XACT interfaces specified
with -from and the -two switches by converting the IP-XACT
interfaces into SV interfaces and instantiating the same in
the current design.
Options :
-from <u_inst1.intf1>, mandatory option to specify the first interface often the one of type Master which drives.
-to <u_inst2.intf2>, mandatory option to specify the second interface often the one of type Slave which gets driven.
-exclude <port1:port2> , optional( use only if you need ) switch
to enlist the logical ports which should be ignored while connecting the interfaces
-v2014 , optional boolean switch to specify that the input IP-XACT version is 2014
-comment <"Inline comments to be printed"> , Provide comments in quotes
which will get printed next to this port mapping.
This option must be used as the last option of this command.
Example : baya_connect_ipxact_interfaces_by_converting_into_sv_interface -from u_Inst1.master_intf -to u_Inst2.slave_intf
[17] Command : baya_exclude_auto_ports
Description: Excludes creation of the auto ports in the top module
corresponding to the given module's port. This command
is useful only when you want to create auto ports in the
top module through the command baya_create_auto_ports .
This command must be called before calling the command baya_create_auto_ports .
Options : -ports <port1:port2>, optional switch to specify the ports to be ignored while creating the auto ports.
You can also pass regular expression as port name, in such case
all the ports matching with that pattern will get excluded from
the auto creation. Note that the char '.' is necessary before the '*' .
In absence of this option, all the ports of the given module will
get ignored while creating the auto ports at the top level.
-module < sub-module name> , mandatory input, to specify the name of the module whose
ports to be excluded for auto creation in the top module
Example : baya_exclude_auto_ports -module leaf -ports port1:port2
baya_exclude_auto_ports -module submod -ports .*
baya_exclude_auto_ports -module bottom
[18] Command : baya_create_auto_ports
Description: Declares/Creates ports in the top module for the component
ports which are not connected while instantiation. This auto
created port is then mapped with the instance port/pin to
establish connection. This command gets effective while
elaborating the design and hence you must elaborate the design
after setting this command before printing or referring.
Options : -exclude <comp1(port1:port2),comp2(port2):comp3(test.*)> , optional switch to specify the ports
to be ignored while creating the auto ports at the top level.
You can also pass regular expression as port name, in such case
all the ports matching with the given pattern of that instance
will get excluded from the auto creation.
Pass .* to exclude all the ports of a given component.
If you want to exclude multiple ports/pins the you can
use the comand baya_exclude_auto_ports before call this command.
Example : baya_create_auto_ports -exclude comp1(port1:port2),comp2(.*)
[19] Command : baya_add_connection
Description: Creates connection between the source port or pin and the destination
port or pin. The source could be a input port of the top module or
output pin of an instance. The destination can be an output of the
top module or input pin of an instance. Also see the command
baya_auto_connect for automatic connections .
Options :
-src <port/pin/interface name> , mandatory option to specify from where the
connection starts
-dest <port/pin/interface name> , mandatory option to specify to where the
connection ends
You can provide multiple destinations separated with comma.
Note that there is not space between the commas.
-ifdef_var <macro name> , optional input, to specify the macro enclosing this port map
-netname <connecting wire name> , optional( use only if you need ) switch
to specify the the name of the connecting wire when
connecting two instance ports/bits/slices. Baya can
internally generate this wire name if user
does not provide this switch. In presence of
this switch, Baya will declare this net in the
current module and establish the connection with this.
-intf_port_maps <formal1@actual1/formal2@actual2>, optional input for the port maps of the interface which will
connect the two instances' interfaces
-intf_param_maps <param1=value/param2=value>, optional input for the parameter maps for the interface which will
connect the two instances' interfaces
-comment <"Inline comments to be printed"> , Provide comments in quotes
which will get printed next to this port mapping.
This option must be used as the last option of this command.
Example : baya_add_connection -src input1 -dest instance_1.in1 -comment "This is comment"
baya_add_connection -src input1 -dest inst1.in1,inst2.in2,out3
baya_add_connection -src inst_1.out1 -dest instance_2.in1[0]
baya_add_connection -src inst_1.out1 -dest out -ifdef_var PWR
baya_add_connection -src inst_1.out1(0) -dest instance_2.in1(3)
baya_add_connection -src inst_1.out1(3:1) -dest instance_2.in1(7:9)
baya_add_connection -src inst_1.out1 -dest instance_2.in1 -netname mynet_out1_in1
baya_add_connection -src inst_1.out1(3:1) -dest instance_2.in1(4:2) -netname p_net1280_addr
baya_add_connection -src inst_1.out1(0) -dest instance_2.in1(3) -netname p_0_1_0_2_a_addr
[20] Command : baya_add_constant_connection
Description: Drives the input pin of an instance or the output port of the
current design/module with the specified constant value.
Options :
-value <constant value> , mandatory option to provide the constant value.
It supports constant values in the verilog format.
Example, 3'b101 or 16'hdead .
-dest <port or pin name> , mandatory option to specify to where the
constant value should get connected/assigned to.
You can provide multiple destinations separated with comma.
Note that there is not space between the commas.
-ifdef_var <macro name> , optional input, to specify the macro enclosing this port map
-comment <"Inline comments to be printed"> , Provide comments in quotes
which will get printed next to this port mapping.
This option must be used as the last option of this command.
Example : baya_add_constant_connection -value 3'b101 -dest instance_1.in1
baya_add_constant_connection -value 16'hdead -dest instance_2.in1
baya_add_constant_connection -value 15.out1 -dest out
baya_add_constant_connection -value 16'hdead -dest inst.in1,inst2.in2,out3
[21] Command : baya_add_empty_connection
Description: Creates empty/open port connection for an instance
Options :
-pin <instance pin name> , mandatory option to specify the
instance pin name to keep open
-ifdef_var <macro name> , optional input, to specify the macro enclosing this port map
-comment <"Inline comments to be printed"> , Provide comments in quotes
which will get printed next to this port mapping.
This option must be used as the last option of this command.
Example : baya_add_empty_connection -pin instance_1.in1
[22] Command : baya_create_hierarchy
Description: Creates a new hierarchy by enclosing the list of instances in the
given module. It internally creates a new module with the name specified
name and then instantiates the given list of instances in that new module.
This way one new hierarchy get created in the given module.
Options :
-insts <instance list> , mandatory option to provide list of instances
separated with comma(,). These instances must be present
in the given module.
-new_inst_name <name> , mandatory option for the new hierarchy name
-new_mod_name <name> , mandatory option for the new module name enclosing the instances
Example : baya_create_hierarchy -insts inst1,inst2,inst3 -new_inst_name newInst -new_mod_name wrapperMod
[23] Command : baya_create_sv_interface_instance
Description: Instantiates an interface inside the current module. The name of the interface which
gets instantiated is specified with the -intf switch. The name of the instance
is specified with the -name switch of this this function.
Options :
-name <interface instance name> , the name of the interface instance to be created.
-intf <interface name> , the name of the bus interface which is to be instantiated
-range <range> , optional switch to specify the range e.g -range 7:0
Example : baya_create_sv_interface_instance -name my_inst_1 -intf ahb_intf
[24] Command : baya_create_sv_structure_object
Description: Instantiates a structure inside the current module. The name of the structure which
gets instantiated is specified with the -structure switch. The name of the instance
is specified with the -name switch of this this function.
Options :
-name <obj name> , the name of the structure instance to be created.
-struct <structure name> , the name of the already defined structure which is to be instantiated
Example : baya_create_sv_structure_object -name my_obj -struct mystructdef
[25] Command : baya_create_instance
Description: Instantiates a module inside the current module. The name of the module which
gets instantiated is specified with the -master switch. The name of the instance
is specified with the -name switch of this this function.
Options :
-name <instance name> , the name of the instance to be created.
-master <master module name> , the name of the Verilog module which is to be instantiated
-vlnv <IP-XACT Component VLNV> , the VLNV of the IP-XACT
Component to be instantiated. The Component will be
picked up from the search path(s). The VLNV should
be '/' separated Vendor, Library, Name, Version e.g.
edautils.com:compLib:uart:1.3
Example : baya_create_instance -name my_inst_1 -master mod1
baya_create_instance -name my_inst_1 -vlnv edautils.com/compLib/uart/1.3
[26] Command : baya_create_instances
Description: Creates multiple instances of same or different modules based upon the colon(:) separated instance&module pairs.
Options :
-insts <instance-module pairs> , comma separated list containing instance name and module name in the brace e.g. inst1(mod1),inst2(mod1),inst3(mod3)
Example : baya_create_instances -insts inst1(mod1),inst2(mod1),inst3(mod3)
This command will create an instance named 'inst1' of the module 'mod1', another instance named 'inst2' of the module 'mod1', an instance named 'inst3' of the module 'mod3' .
[27] Command : baya_create_module
Description: Creates new module with the specified name and sets
as the same current module.
Options :
-name <module name> , the name of the module to be created.
Note that this module will get set as the currrent module/design.
Example : baya_create_module -name mod1
[28] Command : baya_create_local_parameter
Description: Creates a local parameter in the current module or the in the module
specified with the -module switch. The name of the localparam and its
value will be the one passed with the -name and the value switches.
Options :
-name <param name> , mandatory input, the name of the parameter to be created.
-value <param value> , mandatory input, the value of the parameter to be set to.
-module <module name> , optional input, name of the module where this parameter
is to be created. If not specified then the parameter will
get created the current module.
Example : baya_create_local_parameter -name param1 -value 10 -module mod1
[29] Command : baya_create_parameter
Description: Creates a parameter in the current module or the in the module
specified with the -module switch. The name of the parameter and its
value will be the one passed with the -name and the value switches.
Options :
-name <param name> , mandatory input, the name of the parameter to be created.
-value <param value> , mandatory input, the value of the parameter to be set to.
-module <module name> , optional input, name of the module where this parameter
is to be created. If not specified then the parameter will
get created the current module.
Example : baya_create_parameter -name param1 -value 10 -module mod1
[30] Command : baya_create_parameter_map
Description: Overrides a parameter with the new value for the given instance.
It creates a parameter map in the given instance.
Options :
-inst <inst name> , mandatory input, the name of the instance.
-param <param name> , mandatory input, name of the parameter whose
value to be set to.
-value <param value> , mandatory input, the value of the parameter to be set to.
Example : baya_create_parameter_map -inst instance_1 -param param1 -value 10
[31] Command : baya_create_port_map
Description: Creates and then adds a port map in a module or interace instance
Options :
-formal <hierarchical pin name> , mandatory input, to provide
the port name of the interface or module instnace,
example intfref.clk or inst.clk
-actual <value to be associated> , mandatory input to associate
with the specified formal port of the instance or
interface. This value can be a local net or port of
the current design/module
Example : baya_create_port_map -formal inst1.clk -actual wire1
[32] Command : baya_create_interface_map
Description: Creates and then adds an interface map in a module instance
Options :
-formal <hierarchical intf name> , mandatory input, to provide
the interface name of the module instnace, example
u_modem.ahb_intf
-actual <interface reference to be associated> , mandatory
input interface instnace( this can be locally
declared intf instance or current top module's port)
Example : baya_create_interface_map -formal inst1.ahb_intf -actual ahb_intf
[33] Command : baya_create_net
Description: Creates a net in the current module or in the module specified module.
Options :
-name <wire name> , mandatory input, name of the net be created
-range <left-bound:right-bound> , optional input, range for the vector net/bus
-module <module name> , optional input, name of the module where this net
is to be created. If not specified then the net will
get created in the current module.
Example : baya_create_net -module myMod -name net1 -range 2:0
[34] Command : baya_create_port
Description: Creates a port in the current module or in the module specified module.
Options :
-name <port name> , mandatory input, name of the port be created
-dir <in|out|inout> , mandatory input, direction of the port be created
-range <left-bound:right-bound> , optional input, range for the vector port or bus
-module <module name> , optional input, name of the module where this port
is to be created. If not specified then the port will
get created in the current module.
Example : baya_create_port -module myMod -name port1 -dir in -range 2:0
[35] Command : baya_create_port_user_defined_type
Description: Creates a port in the current module or in the module specified module.
Options :
-name <port name> , mandatory input, name of the port be created
-dir <in|out|inout> , mandatory input, direction of the port be created
-type <typename> , mandatory input to specify the data-type name e.g. structure name
-module <module name> , optional input, name of the module where this port
is to be created. If not specified then the port will
get created in the current module.
Example : baya_create_port_user_defined_type -name port1 -dir in -type mystruct_t
Use the command baya_add_ranges_or_dimensions_in_object to add packed/unpacked dimension(s) to this port.
[36] Command : baya_add_ranges_or_dimensions_in_object
Description: Adds the given comma separated ranges in the packed or unpacked
dimension list of the specified port or net
Options :
-name <name> , mandatory input, name of the port or net where
the given ranges is to be added
-ranges 1:0,3:0 , mandatory input, comma separated ranges to
be added in the dimension list
-packed , optional boolean switch to specify if the given
ranges belong to 'packed' dimension list. In absence
of this switch, the given ranges will be added in
the uppacked dimension list.
-module <module name> , optional input, name of the module
where this port belongs. If not specified then the
port will get searched in the current module.
Example : baya_add_ranges_or_dimensions_in_object -module myMod -name port1 -packed ranges 7:0,3:0
baya_add_ranges_or_dimensions_in_object -name net1 -ranges 7:0,3:0
[37] Command : baya_create_port_sv_interface_type
Description: Creates interface type port in the current module or in the module specified module.
Options :
-name <port name> , mandatory input, name of the port be created
-type <typename> , mandatory input to specify the data-type name e.g. structure name
-range <7:0> , optional input to specify range
-module <module name> , optional input, name of the module where this port
is to be created. If not specified then the port will
get created in the current module.
Example : baya_create_port_sv_interface_type -name port1 -type bus_intf.modport
[38] Command : baya_elaborate
Description: Elaborates a module
Options :
-module <module name> , optional input, name of the module which
is to be elaborated. The current module be elaborated
if the this switch is not provided.
Example : baya_elaborate -module myMod
[39] Command : baya_elaborate_root
Description: Elaborates a design database root
Options :
Example : baya_elaborate_root
[40] Command : baya_find_all_gate_instances
Description: Returns list of verilog primitive gate instances in the current module.
Options :
Example : baya_find_all_gate_instances
[41] Command : baya_find_all_module_instances
Description: Returns list of module instances in the current module.
Options :
Example : baya_find_all_module_instances
[42] Command : baya_find_all_udp_instances
Description: Returns list of udp instances in the current module.
Options :
Example : baya_find_all_udp_instances
[43] Command : baya_find_all_modules
Description: Returns list of all modules in the current design database in the memory.
Options :
Example : baya_find_all_modules
[44] Command : baya_find_all_nets
Description: Returns list of nets in the current module.
Options :
Example : baya_find_all_nets
[45] Command : baya_find_all_ports
Description: Returns list of ports of the current module.
Options :
Example : baya_find_all_ports
[46] Command : baya_find_gate_instances
Description: Returns list of verilog primitive instances with name matching
with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the instance names
Example : baya_find_gate_instances -name ".*"
[47] Command : baya_find_hier_gate_instances
Description: Returns list of verilog primitive instances with hierarchical name
matching with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match the
hierarchical instance names
Example : baya_find_hier_gate_instances -name ".*"
[48] Command : baya_find_hier_module_instances
Description: Returns list of verilog module instances with hierarchical
name matching with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the hierarchical instance names
Example : baya_find_hier_module_instances -name ".*"
[49] Command : baya_find_hier_nets
Description: Returns list of hierarchical nets with name matching with the
regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the hierarchical net names
Example : baya_find_hier_nets -name ".*"
[50] Command : baya_find_hier_ports
Description: Returns list of hierarchical ports/pin with name matching with
the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the hierarchical port names
Example : baya_find_hier_ports -name ".*"
[51] Command : baya_find_hier_udp_instances
Description: Returns list of verilog udp instances with hierarchical name
matching with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the hierarchical instance names
Example : baya_find_hier_udp_instances -name ".*"
[52] Command : baya_find_gate_instances
Description: Returns list of verilog primitive instances with name matching
with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the instance names
Example : baya_find_gate_instances -name ".*"
[53] Command : baya_find_module_instances
Description: Returns list of verilog module instances with name matching
with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the instance names
Example : baya_find_module_instances -name ".*"
[54] Command : baya_find_nets
Description: Returns list of nets with name matching with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the net names
Example : baya_find_nets -name ".*"
[55] Command : baya_find_ports
Description: Returns list of ports with name matching with the regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the port names
Example : baya_find_ports -name ".*"
[56] Command : baya_find_udp_instances
Description: Returns list of udp instances with name matching with the
regular expression
Options :
-name <pattern or regular expression> , mandatory input, to match
the instance names
Example : baya_find_udp_instances -name ".*"
[57] Command : baya_import_ipxact
Description: Reads the specified IP-XACT component or design xml file
Options :
-component <IP-XACT component XML file name> , Component XML
-design <IP-XACT Design XML file name> , Design XML , you
should specify the component with the -component
switch corresponding to this design in order to create
the ports/params in the generated Verilog/VHDL design
-merge_mmap , optional boolean switch to specify that memory
from this Component needs to be merged with the
previously loaded component with same name as this
Default false and useful only with the -component switch.
Example : baya_import_ipxact -component foo.component.xml
baya_import_ipxact -design Leon_Design.xml -component Leon.xml
[58] Command : baya_ipxact_add_component
Description: Adds the specified IP-XACT component object on the database
Options :
-component <IP-XACT Component> , Component type object
-merge_mmap , optional boolean switch to specify that memory
from this Component needs to be merged with the
previously loaded component with same name as this
Default false
Example : baya_ipxact_add_component -component $compObj
[59] Command : baya_ipxact_component_add_memorymap
Description: Inserts the given IP-XACT MemoryMap into the specified Component
Options :
-component <Component VLNV> , the VLNV in separated with '/' of the
Component inside which the given MemoryMap to be inserted.
If you want to associate Memory Map with a Verilog Module,
then just pass the name of the Module which is already imported in the database.
-xml <AddrBlk.xml> , switch to specify the IP-XACT file containing the MemoryMap(s) or AddressBlock which is to be inserted
Example : baya_ipxact_component_add_memorymap -component synopsys/lib/DDR/1.5 -xml mmap.xml
[60] Command : baya_ipxact_component_object_add_memorymap
Description: Inserts the given IP-XACT MemoryMap into the specified Component Object
Options :
-component <Component Object> , the Component Object
-xml <AddrBlk.xml> , switch to specify the IP-XACT file containing the MemoryMap(s) or AddressBlock which is to be inserted
Example : baya_ipxact_component_object_add_memorymap -component $compObj -xml mmap.xml
[61] Command : baya_ipxact_component_object_add_memorymap
Description: Inserts the given IP-XACT MemoryMap into the specified Component Object
Options :
-component <Component Object> , the Component Object
-xml <AddrBlk.xml> , switch to specify the IP-XACT file containing the MemoryMap(s) or AddressBlock which is to be inserted
Example : baya_ipxact_component_object_add_memorymap -component $compObj -xml mmap.xml
[62] Command : baya_ipxact_convert_verilog_module_into_component
Description: Creates IP-XACT component corresponding to a Verilog Module
Options :
-module <Module Name> , name of the module which is to be converted into IP-XACT Component
Example : baya_ipxact_convert_verilog_module_into_component -module i2c
[63] Command : baya_generate_rsa_keys
Description: Generate public and private key files
Options :
-pvtkey <file name>, input to specify the private key file name
-pubkey <file name>, input to specify the public key file name
Example : baya_generate_rsa_keys -pvtkey key.pvt.dat -pubkey key.pub.dat
[64] Command : baya_preprocess_verilog
Description: Reads the given input file and writes back the preprocessed
output file
Options :
-in <input file name> , mandatory input, to specify the
input file name
-out <ioutput file name> , mandatory input, to specify the
output file name
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-pubkey <public key file> input to pass the public keyfile
with which the data will get decrypted.
This input is mandatory for decryption.
-key <key for encrytption> , input to pass the key with which
the data will get encrypted. This input
is must while encryption and not
required while decrypting an encrypted
file. However, the private is must in
order to decrypt a file.
-pvtkey <private keyfile name> , to specify the name of the
private key file. This input is must
in order to decrypt an encrypted input
file. It is optional when you call this
to encrypt a file. While encryption,
the private key will get dumped in this
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-commented , optional boolean switch to specify if
the 'protect' directives should be inside
the '//' instead of the '`pragma'. By default
its false.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example (for encryption) : baya_preprocess_verilog -in foo.v -out processed.v -incdir dir1+dir2 -definedir define+macro1+macro2 -key edautils_dot_com -pubkey pubkey.dat -keyowner SiliconIndia -keyname SI_001
Example(for decryption) : baya_preprocess_verilog -in foo.v -out processed.v -incdir dir1+dir2 -definedir define+macro1+macro2 -pvtkey pvtkey.dat -keyowner SiliconIndia -keyname SI_001
[65] Command : baya_import_verilog
Description: Imports the specified verilog file so that the module can be instantiated.
Options :
-file <file name> , mandatory input, file to be read
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <module to be imported> , mandatory input, top module in this file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command baya_generate_rsa_keys
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : baya_import_verilog -file foo.v -top myTop -incdir dir1+dir2 -definedir define+macro1+macro2
[66] Command : baya_import_verilog_filelist
Description: Imports the specified multiple verilog files listed in the input file
Options :
-filelist <list file> , mandatory input, file where verilog files
are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <module to be imported> , mandatory input, top module in this file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command baya_create_rsa_keys .
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : baya_import_verilog_filelist -filelist infile.list -top myTop -incdir dir1+dir2 -definedir define+macro1+macro2
[67] Command : baya_import_verilog_file_list
Description: Imports the specified multiple verilog files listed in the input file
Options :
-file_list <list file> , mandatory input, file where verilog files
are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <module to be imported> , mandatory input, top module in this file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command baya_create_rsa_keys .
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : baya_import_verilog_file_list -file_list infile.list -top myTop -incdir dir1+dir2 -definedir define+macro1+macro2
[68] Command : baya_import_vhdl
Description: Imports the specified VHDL file
Options :
-file <VHDL file name> , mandatory input, name of the VHDL to be read
-top <entity to be imported> , mandatory input, entity defined in this file
-work <work lib name> , optional input, to specify the work library
-mapfile <map file> , optional input, logical to physical library
map file. Each line in this mapfile should
be similar to below.
WORK=/home/klg/vhdl_dumps/work
GATE=/home/klg/vhdl_dumps/gatelib
CORE=/home/klg/vhdl_dumps/core
Example : baya_import_vhdl -file foo.vhd -work work -mapfile libmap.ini
[69] Command : baya_import_vhdl_filelist
Description: Imports the specified VHDL file
Options :
-filelist <VHDL filelist name> , mandatory input, name of the VHDL filelist
-top <entity to be imported> , mandatory input, entity defined in this file
-work <work lib name> , optional input, to specify the work library
-mapfile <map file> , optional input, logical to physical library
map file. Each line in this mapfile should
be similar to below.
WORK=/home/klg/vhdl_dumps/work
GATE=/home/klg/vhdl_dumps/gatelib
CORE=/home/klg/vhdl_dumps/core
Example : baya_import_vhdl_filelist -file foo.vhd -work work -mapfile libmap.ini
[70] Command : baya_import_mixed_hdl_filelist
Description: Imports the specified multiple Verilog and VHDL files listed in the input list file
Options :
-filelist <list file> , mandatory input, file where VHDL and
Verilog files are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <module to be imported> , mandatory input, top module in this file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
Example : baya_import_mixed_hdl_filelist -filelist infile.list -top myTop -incdir dir1+dir2 -definedir define+macro1+macro2
[71] Command : baya_set_ansi_header_print_verilog
Description: Disable/enable ANSI style header while printing the verilog modules
Options :
-value <true|false> , mandatory input - only true or false is allowed
Example : baya_set_ansi_header_print_verilog -value false
[72] Command : baya_print_verilog
Description: Prints the current module or the one specified with the switch -module
Options :
-module <module name> , optional input, name of the module which
is to be printed. The current module be
printed if the this switch is not provided.
-key <key for encrytption> , input to pass the key with which
the data will get encrypted. This input
is must while encryption and not
required while decrypting an encrypted
file. Howver, the private is must in
order to decrypt a file.
-pubkey <public keyfile name> , to specify the name of the
public key file
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-commented_directive , optional boolean switch to specify if the
'protect' directives to be printed
as '// protect ...' . Default is
false and by default it'll print the same
as '`pragma protect ...'
Example : baya_print_verilog -key edautils_dot_com -pubkey publickey.dat -keyowner SiliconIndia -keyname SI_001
[73] Command : baya_print_verilog_file
Description: Prints the current module or the one specified with the
switch -module in the file set with baya_set_file command.
In other words, this saves the DB as verilog log database.
This is implementation of baya_save_as_verilog_file command.
Options :
-module <module name> , optional input, name of the module which
is to be printed. The current module be
printed if the this switch is not provided.
-file <file name> , optional input to specify the file name
-key <key for encrytption> , input to pass the key with which
the data will get encrypted. This input
is must while encryption and not
required while decrypting an encrypted
file. Howver, the private is must in
order to decrypt a file.
-pubkey <public keyfile name> , to specify the name of the
public key file
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-commented_directive , optional boolean switch to specify if the
'protect' directives to be printed
as '// protect ...' . Default is
false and by default it'll print the same
as '`pragma protect ...'
Example : baya_print_verilog_file -key edautils_dot_com -pubkey publickey.dat -keyowner SiliconIndia -keyname SI_001 -file output.v
[74] Command : baya_print_empty_module
Description: Prints the specifiled module or the current module in the file.
Options :
-module <module name> , name of the module which is to be
printed by stripping the functionality
-file <file name> , optional input to specify the file name
-no_includes , optional boolean switch to disable printing
of the include files.
Example : baya_print_empty_module -module foo -file foo.nobody.v
[75] Command : baya_print_csv_for_integration
Description: Prints integration intent( input ports ) of the module or the current module in the file.
Options :
-module <module name> , name of the module for which CSV to be printed
-file <file name> , the CSV file name where inputs pins, params to be listed
Example : baya_print_csv_for_integration -module foo -file foo.csv
[76] Command : baya_print_vhdl
Description: Prints in VHDL the current module or the one specified with
the switch -module .
Options :
-module <module name> , optional input, name of the module which
is to be printed. The current module be
printed if the this switch is not provided.
Example : baya_print_vhdl -module myMod
[77] Command : baya_print_vhdl_file
Description: Prints in VHDL the current module or the one specified with the
switch -module in the file set with baya_set_file command.
Options :
-module <module name> , optional input, name of the module which
is to be printed. The current module be
printed if the this switch is not provided.
-file <file name> , optional input, to specify the file name
where the given module or the currently
active module needs to printed.
Example : baya_print_vhdl_file -module myMod [-file foo.vhd]
[78] Command : baya_generate_ipxact_component_c_model
Description: Creates C/H model corresponding to the specified IP_XACT component which is already imported into the database
Options :
-component <component name> , name of the component which needs to be translated into C/H Model
-reg_value_accssor <name> , optional switch to specify the name of
the accessor corresponding to REGISTER value, default is 'value' ,
get reg value as <reg name>.value
-reg_field_accssor <name> , optional switch to specify the name of the accessor
corresponding to REGISTER Bit Fileds, default is 'Fields' ,
get reg bit-fields as <reg name>.Fields
-v2014 , optional boolean switch to specify that the input IP-XACT version is 2014
-outdir <dir path> , output directory name where the C/H files need to be dumped
Example : baya_generate_ipxact_component_c_model -component i2c -outdir csrc
[79] Command : baya_generate_ipxact_design_c_model
Description: Creates C/H model corresponding to the specified IP-XACT Design or the current top design where IP-XACT components have been instantiated
Options :
-design <design name> , name of the design which needs to be translated into C/H Model
-mapfile <baseaddr.map> , the base address map file where each line
contains the overridden base address corresponding to
each instance's AddressBlock in the design. Example,
instance_1/mmap1/addrblk1 = 0x00001024
instance_2/mmap1/addrblk1 = 0x00002048
instance_2/mmap2/addrblk1 = 0x00003072
-v2014 , optional boolean switch to specify that the input IP-XACT version is 2014
-outdir <dir path> , output directory name where the C/H files need to be dumped. Default directory is c_model
-reg_value_accssor <name> , optional switch to specify the name of
the accessor corresponding to REGISTER value, default is 'value' ,
get reg value as <reg name>.value
-reg_field_accssor <name> , optional switch to specify the name of the accessor
corresponding to REGISTER Bit Fileds, default is 'Fields' ,
get reg bit-fields as <reg name>.Fields
-uniquify , boolean switch to uniquify the struct names based
upon the overidden config. element values in the
component instantion. Useful if same component gets
instantiatied multiple times with different
register/memory configuration(s) . Default is false
Example : baya_generate_ipxact_design_c_model -design Leon -mapfile baseAddr.map -outdir csrc
[80] Command : baya_ipxact_design_get_all_address_block_hierarchical_names
Description: Returns a list of all address block ahierarchical names from the specified IP-XACT Design name ( ijust the name, not VLNV )
Options :
-design <design name> , name of the design from which the address blocks need to reported
Example : baya_ipxact_design_get_all_address_block_hierarchical_names -design Leon
[81] Command : baya_remove_connection
Description: Removes connection between the source port or pin and the destination
port or pin. The source could be a input port of the top module or
output pin of an instance. The destination can be an output of the
top module or input pin of an instance.
Options :
-src <port or pin name> , mandatory option to specify from where
the connection starts
-dest <port or pin name> , mandatory option to specify to where
the connection ends
Example : baya_remove_connection -src input1 -dest instance_1.in1
baya_remove_connection -src inst_1.out1 -dest instance_2.in1
baya_remove_connection -src inst_1.out1 -dest out
[82] Command : baya_remove_hierarchy
Description: Removes a hierarchy by flattening the the specified instance in the
current module. It internally pulls up the contents of the instance
in the current module.
Options :
-inst <instance name> , mandatory option to provide the instance
-all_levels , optional boolean switch to specify if the hierarchy
of the subsequent lower levels to be removed
Example : baya_remove_hierarchy -inst inst1 -all_levels
[83] Command : baya_remove_instance
Description: Removes the instance specified with the -name switch from the current module.
Options :
-name <instance name> , the name of the instance to be removed.
Example : baya_remove_instance -name inst1
[84] Command : baya_get_maturity_status
Description: Calculates the RTL maturity status w.r.t connection of the instances
Options :
-module <design name> , optional input to specify the design.
Example : baya_get_maturity_status -module foo
[85] Command : baya_create_wrapper_verilog_in_verilog
Description: Creates a Verilog wrapper module by instantiating the specified
module.
Options :
-module <module name>, mandatory input to specify the module
name around which the wrapper needs to
be generated.
-flatten , optional boolean switch to enable the splitting of
the multidimensional port arrays
-wrapper <module name> optional switch to specify the name
of the wrapper module to be created.
-outfile <file name> optional switch to specify the name
of the output file where the wrapper module will
be written
Returns : The wrapper module object
Example : baya_create_wrapper_verilog_in_verilog -module originalModule -wrapper wrapperModule -flatten -outfile wrapperModule.sv
[86] Command : baya_create_wrapper_vhdl_in_vhdl
Description: Creates a VHDL wrapper module by instantiating the specified
entity.
Options :
-entity <entity name>, mandatory input to specify the entity
name around which the wrapper needs to
be generated.
-wrapper <entity name> optional switch to specify the name
of the wrapper entity to be created.
-outfile <file name> optional switch to specify the name of the output file where the
wrapper entity and architecture will be written
-work <library name> , optional input to specify the library
from where this entity to be loaded.
Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : The wrapper entity object
Example : baya_create_wrapper_vhdl_in_vhdl -entity originalEntity -wrapper wrapperEntity -outfile wrapper.vhd
[87] Command : baya_clean_vhdl_design_database
Description: Cleans up the internal design database for fresh parsing of
vhdl design units. This is would be required when comparing
two entities with same name. You should parse the files
containing the golden entity/arch and then clean up the
design database to avoid the multiple definition error and
then parse the revised RTL file(s) containing the modified
definition of the same entity/arch.
Options : None
Returns : None
Example : baya_clean_vhdl_design_database
[88] Command : baya_clean_verilog_design_database
Description: Cleans up the internal design database for fresh parsing of
modules. This is would be required when comparing two modules
with same name. You should parse the files containing the
golden module and then clean up the design database to avoid
the multiple definition error and then parse the revised RTL
file(s) containing the modified definition of the same module.
Options : None
Returns : None
Example : baya_clean_verilog_design_database
[89] Command : baya_set_hdl_search_path
Description: Colon separated paths where the Veriloh/VHDL files to be searched
Options :
-paths <colon separated paths> , mandatory input to specify the
paths where from the referred VHD/Verilog file
should be picked up
Returns : None
Example : baya_set_hdl_search_path -paths /edautils/install:.
[90] Command : baya_set_ipxact_search_path
Description: Colon separated paths where the components to bearched as
per the VLNV
Options :
-paths <colon separated paths> , mandatory input to specify the
paths where from the IP-XACT components/design/
busedfs be loaded as per the VLNV. This must be
used in the beginning or before loading component
or design XML.
-v2014 , optional boolean switch to specify that the input IP-XACT version is 2014
Returns : None
Example : baya_set_ipxact_search_path -paths /edautils/install:.
[91] Command : baya_verilog_find_module
Description: Searches for the modules matching with the regular
expression
Options :
-name <module name> , mandatory input to specify the
module name which needs to be searched in the
design database
Returns : The module object matching with the name
Example : baya_verilog_find_module -name foo
[92] Command : baya_vhdl_find_entity
Description: Returns the VHDL entity with the specified name
Options :
-name <entity name> , mandatory option to specify the entity
name to be loaded
-work <library name> , optional input to specify the library
from where this entity needs to be
loaded. Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the VHDL entity object
Example : baya_vhdl_find_entity -name foo [-work WORK] [-mapfile map.ini ]
[93] Command : baya_compare_verilog_modules
Description: Compare two verilog module's parameter's, ports, interfaces and instances
Options :
-golden <golden module name>, mandatory input to specify the golden
module name. You must invoke the command
baya_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-revised <revised module name>, mandatory input to specify the revised
module name. You must invoke the command
baya_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-ignore_insts , optional boolean switch to ignore comparsion of instanc(s), use this switch
if you want to compare only the ports and parameters
-ignore_assgns , optional boolean switch to ignore comparsion of concurrent statements, use this switch
if you want to compare only the ports and parameters
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : baya_compare_verilog_modules -golden mod_gld -revised mod_rev -outcsv foo.csv -outtxt bar.txt
[94] Command : baya_compare_verilog_module_objects
Description: Compare two verilog module's parameter's, ports, interfaces and instances
Options :
-golden <golden module object>, mandatory input to specify the golden
module object. You must invoke the command
baya_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-revised <revised module object>, mandatory input to specify the revised
module object. You must invoke the command
baya_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-ignore_insts , optional boolean switch to ignore comparsion of instanc(s), use this switch
if you want to compare only the ports and parameters
-ignore_assgns , optional boolean switch to ignore comparsion of concurrent statements, use this switch
if you want to compare only the ports and parameters
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : baya_compare_verilog_module_objects -golden mod_gld -revised mod_rev -outcsv foo.csv -outtxt bar.txt
[95] Command : baya_merge_modules
Description: Merges contents of two definitions of same module where two different sets of instances were grouped independently. This command will put them together as if both the group commands were executed in the same run.
Options :
-top <top module name>, mandatory input to specify the top module name
-instances <colon-separated-instances>, List of instances names separated with colon. Specify only instance name if the containing module name is same as 'top' otherwise specify the module name with '@' e.g. inst1@foo_mod
-seed_inst <instance name>, optional input to specify the seed instance name. All other grouped instances from other modueles will be pulled here.
-infile <verilog file name containing modules>, mandatory input to provide the module definition. Do not use this switch if you have multiple files, use -filelist in such case
-filelist <list file> , specify multiple files throug this switch. You to specify +incdir or +define directivies as applicable
-excludefilelist <list file> , optional switch to specify files to excluded from parsing while -filelis is used
-wildcard , optional boolean switch to accept wildcards in file name, try not to use this switch if you can
-noreparse , disables reparse of the merged module. By default, it save the merged module into a file are reparse it after every mering. Thouh it increases the runtime, it creates fresh symbol table.
-outfile <file name>, swicth to specify the output file name where the merged module will be saved
Returns : None
Example : baya_merge_modules -top top -instances new_hier1:new_hier2@anothertop:new_hier3 -seed_inst new_hier5 -outfile merged.v
[96] Command : baya_clean_vhdl_design_database
Description: Cleans up the internal design database for fresh parsing of
vhdl design units. This is would be required when comparing
two entities with same name. You should parse the files
containing the golden entity/arch and then clean up the
design database to avoid the multiple definition error and
then parse the revised RTL file(s) containing the modified
definition of the same entity/arch.
Options : None
Returns : None
Example : baya_clean_vhdl_design_database
[97] Command : baya_compare_vhdl_entities
Description: Compare two vhdl entity's generics, ports and instances in the
architectures( most recently compiled architecture )
Options :
-golden <golden entity name>, mandatory input to specify the golden
entity name. You must invoke the command
baya_clean_vhdl_design_database in between reading
the golden and the revised VHDL files.
You should compile the golden RTLs in golden library
and revised RTLs in the revised library if the entity
names are same
-revised <revised entity name>, mandatory input to specify the revised
entity name. You must invoke the command
baya_clean_vhdl_design_database in between reading
the golden and the revised Verilog files
Note: You should compile the golden RTLs in golden library
and revised RTLs in the revised library if the entity
names are same
-golden_work <golden work library name>, mandatory input to specify the golden work( logical )
library name. Make sure that this library was used with
the -work switch while reading/analyzing/importing the RTLs
containing the golden entity/arch. Also ensure that your
specified library exists in the mapfile passed through the -mapfile switch
-revised_work <revised work library name>, mandatory input to specify the revised work( logical )
library name. Make sure that this library was used with
the -work switch while reading/analyzing/importing the RTLs
containing the revised entity/arch. Also ensure that your
specified library exists in the mapfile passed through the -mapfile switch
-mapfile <mapfile name>, mandatory input to specify the VHDL library mappings.
This map file needs to be created by the user thought any text editor.
Each line should contain one library mapping, example-
revised_wrk=/user/klg/vhdl/work/revised
golden_wrk=/user/klg/vhdl/work/golden
If your mapfile contains above two lines, then you can specify
revised_wrk for the -revised_work and golden_wrk for the -golden_work
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : baya_compare_vhdl_entities -golden gld_entity -revised modified_ent -golden_work work1 -revised_work work2 -mapfile mapfile.ini -outcsv diff.csv -outtxt diff.txt
[98] Command : baya_compare_vhdl_entity_objects
Description: Compare two VHDL entity objects- ports, interfaces and instances
Options :
-golden <golden entity object>, mandatory input to specify the golden
entity object. You must invoke the command
baya_clean_vhdl_design_database in between reading
the golden and the revised VHDL files
-revised <revised entity object>, mandatory input to specify the revised
entity object. You must invoke the command
baya_clean_vhdl_design_database in between reading
the golden and the revised VHDL files
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : baya_compare_vhdl_entity_objects -golden gld_ent -revised rev_ent -outcsv foo.csv -outtxt bar.txt
[99] Command : baya_disable_connection_db
Description: Disables creation and population of the Baya connection database
Options :
Example : baya_disable_connection_db
[100] Command : baya_load_connection_db
Description: Loads the specified connection database to extract connection details
Options :
-xml <BayaConnDB.xml>, mandatory input to specify the Baya
connection DB to be loaded. You need to set this
as current Connection DB if you want to get it updated
while creating new Baya connection .
Returns : The BayaConnectionDB object corresponding to the specified file
Example : baya_load_connection_db -xml BayaConnDB.xml
[101] Command : baya_set_current_connection_db
Description: Sets the specified Connection DB Object as the current DB
so that new connections gets added into this database.
Options :
-db <BayaConnDB Object>, mandatory input to specify the Baya
connection DB to be loaded. You need to set this
as current Connection DB if you want to get it updated
while creating new Baya connection .
Returns : None
Example : baya_set_current_connection_db -db BayaConnDBObject
[102] Command : baya_get_current_connection_db
Description: Returns the currently active Baya Connection DB
Options :
Returns : The currently active Baya Connection DB object
Example : baya_get_current_connection_db
[103] Command : baya_get_connected_instances
Description: Returns list of Baya Instances connected with the given
instances. Each item in the list of type BayaInstance
Returned Instances are extracted from the currently
active Connection DB
Options :
-inst <Instance Name>, the first instance name
Returns : List of the Baya Instance Objects
Example : baya_get_connected_instances -inst u_inst
[104] Command : baya_get_connections_between_instances
Description: Returns list of Baya connection object between instances.
Returned connections are extracted from the currently
active Connection DB
Options :
-insts <inst1:inst2 >, colon separated list of instances
Returns : List of the Baya Connection Objects
Example : baya_get_connections_between_instances -insts inst1:inst2
[105] Command : baya_get_connections_between_two_instances
Description: Returns list of Baya connection object between two instances.
Returned connections are extracted from the currently
active Connection DB
Options :
-inst_1 <Instance Name>, the first instance name
-inst_2 <Instance Name>, the second instance name
Returns : List of the Baya Connection Objects
Example : baya_get_connections_between_two_instances
[106] Command : baya_get_connections_between_instance_and_top
Description: Returns list of Baya connection object between instance and top
Returned connections are extracted from the currently
active Connection DB
Options :
-inst <Instance Name>, the instance name
Returns : List of the Baya Connection Objects
Example : baya_get_connections_between_instance_and_top
[107] Command : baya_get_bayadb_instance_name
Description: Returns the name of the specified Baya DB instance
Options :
-inst <Instance Object>, the instance Object
Returns : Instance name
Example : baya_get_bayadb_instance_name -inst instObject
[108] Command : baya_save_as_ipxact_design
Description: Saves the current verilog module or the specified module
as IP-XACT Design.
Options :
-xml <Design.xml>, mandatory input to specify the file
name where the currently active design needs to be
saved as IP-XACT Design file. The specified file
must have .xml extension.
-v2014 , optional boolean switch to enable IP-XACT version is 2014
-module <module name>, optional input to specify the
module name to be saved as IP-XACT
Design ,in absence of this switch the
currently active design will be saved
Returns : None
Example : baya_save_as_ipxact_design -xml BayaConnDB.xml -module MMSS
[109] Command : baya_save_connection_db
Description: Saves the currently active connection database into the specified XML file, must have .xml extension
Options :
-xml <BayaConnDB.xml>, mandatory input to specify the file
name where the currently active Baya connection DB.
The specified file must have .xml extension.
Returns : None
Example : baya_save_connection_db -xml BayaConnDB.xml
[110] Command : baya_get_ipxact_connections_between_two_instances
Description: Returns the list of IP-XACT connections between two instances
The returned connections gets extracted from the given
IP-XACT Design object. You can get the IP-XACT Design object
by loading it explicity preferably along with associated
IP-XACT component. In worst case, if the IP-XACT Design and
Component is not available but the Verilog Module is available,
then generate the IP-XACT Design & Compoent through the
verilog2ipxact tool from EDAUtils.
Options :
-design <IP-XACT Design Object>, mandatory input to specify the
IP-XACT Design Object from where connections to be
extracted
-inst_1 <Instance Name>, the first instance name
-inst_2 <Instance Name>, the second instance name
Returns : List of the IP-XACT Connection Objects between the
Example : baya_get_ipxact_connections_between_two_instances
[111] Command : baya_get_ipxact_connections_between_instance_and_top
Description: Returns the list of IP-XACT connections between an instance
and the top design.
Options :
-design <IP-XACT Design Object>, mandatory input to specify the
IP-XACT Design Object from where connections to be
extracted
-inst <Instance Name>, the instance name
Returns : List of the IP-XACT Connection Objects
Example : baya_get_ipxact_connections_between_instance_and_top
[112] Command : baya_import_connectivity_from_modular_csv_dir_and_partition
Description: Reads the specified Baya connectivity from modular CSV file and
updates those as per the par the partition defintion( JSON ).
Creates new CSV corresponding to the connectivity of the partitions.
Then imports those updated/additional CSV files to create partitions
and connect those.
Options :
-top <top-name>, Top module name i.e name of the SOC/SubSystem module
-dirs <dr1:dir2> Colon separated directories containing CSV files for each module instance.
The CSV file would be like <inst name>.<module name>.csv .
If the <inst name> is not provided i.e. the CSV file name is
like <module name>.csv then the instance name will be created
as u_<module name> . YOu just need to provide connectivity
of the input pins of the module for which CSV is given.
-par <par.json> JSON file containing partition definition
-outdir <outcsv> optional, directory where updated/additional CSV to be written
-outtcl <output.tcl> , optional switch, the output
Tcl file name which to be created by translating
the CSV files inside the input CSV directory.
Example : baya_import_connectivity_from_modular_csv_dir_and_partition -top mytop -dirs csv1:csv2 -par par.json -outdir csvpar -outtcl output.tcl
[113] Command : baya_import_connectivity_from_modular_csv_dir
Description: Reads the specified Baya connectivity from modular CSV file and
creates corresponding Baya Tcl commands and the same gets
executed to establish the connections. Expectation is that for each
instance, the INPUT port's connectivity is provided along with parameter
override as needed.
Options :
-dirs <dir1:dir2>,Colon separated directories containing CSV files for each module instance.
The CSV file would be like <inst name>.<module name>.csv .
If the <inst name> is not provided i.e. the CSV file name is
like <module name>.csv then the instance name will be created
as u_<module name> . YOu just need to provide connectivity
of the input pins of the module for which CSV is given.
-csvfiles <mod1.csv:dir/mod2.csv>, To provide CSV modular files containing connectivity details.
You must specify CSV files either through the -csvfiles or
through the -dirs switch
-outtcl <output.tcl> , optional switch, the output
Tcl file name which to be created by translating
the CSV files inside the input CSV directory.
Example : baya_import_connectivity_from_modular_csv_dir -dirs csv1:csv2 -csvfiles foo.csv:bar.csv -outtcl output.tcl
[114] Command : baya_import_connectivity_csv
Description: Reads the specified Baya connectivity CSV/XLS/XLSX file and
creates corresponding Baya Tcl commands and the same gets
executed to establish the connections.
Options :
-file <connections.csv|connections.xls|connections.xlsx> ,
mandatory input, Baya connectivity CSV/XLS/XLSX file,
see the template in the bin directory
-outtcl <connections.out.tcl> , optional switch, the output
Tcl file name which to be created by translating
the input CSV/XLS/XLSX file
Example : baya_import_connectivity_csv -file connections.csv -outtcl conn.tcl
[115] Command : baya_generate_connectivity_db_from_csv
Description: Reads the specified Baya connectivity CSV/XLS/XLSX file and
creates corresponding Baya Connection DB XML file which can
reused further and queried to extract information.
Options :
-file <connections.csv|connections.xls|connections.xlsx> ,
mandatory input, Baya connectivity CSV/XLS/XLSX file,
see the template in the bin directory
-outxml <BayaConnections.xml> , switch to specify the output
connectivity databse XML file name
Example : baya_generate_connectivity_db_from_csv -file connections.csv -outxml BayaConnectionDB.xml
[116] Command : set_root
Description: Sets the specified module name as the root module
Options :
<module name> , mandatory argument to specify the module name as root module
Example : set_root topMod
[117] Command : ls
Description: lists down all the objects
Options :
-p , optional boolean switch to enable the port listing
-n , optional boolean switch to enable the net listing
-i , optional boolean switch to enable the instance listing
-h , optional boolean switch to enable hierarchical objects
<pattern> , optional inout to specify the pattern to be matched
Example : ls -i -h /top/inst1/inst*
[118] Command : cd
Description: changes current working module to the specified hierarchical path
Options :
<hierarchical instance name> , mandatory argument to specify the hierarchical instance path.
Example : cd /top/inst1/inst2
[119] Command : mkdir
Description: creates the specified hierarchical instance corresponding to the specified module
Options :
<hierarchical instance name> , mandatory argument to specify the hierarchical instance to be created.
-m <module name> , mandatory input, the name of the module which is to be instantiated
Example : mkdir /top/inst1/inst2 -m mod1
[120] Command : pwd
Description: returns the hierarchical instance path which is being considered as current working module.
[121] Command : rm
Description: removes the specified hierarchical instance from the design database
Options :
<hierarchical instance name> , mandatory argument to specify the hierarchical instance to be deleted.
Example : rm /top/inst1/inst2
[122] Command : rename
Description: renames the specified object to the given name
Options :
<current name> , mandatory argument to specify the current name which needs to be renamed
<new name> , mandatory argument to specify the new name
Example : rename /top/inst1/inst2 /top/inst1/newInst
[123] Command : ipxact_set_description
Description: Attaches the given description with the specified IP-XACT object
Options :
$object , mandatory input which is the IP-XACT object created through commands/APIs.
Some of the example objects could be component, bus definition, abstraction
definition, memory map, register etc.
description, mandatory input, the string containing the description for the object
Returns : Returns updated object
Example : ipxact_set_description $componentObject "This component has been generated with the free IP-XACT utility from edautils.com ."
[124] Command : ipxact_create_component
Description: Creates an IP-XACT component with the given details
Options :
-name <comp name> , mandatory option to specify the component name.
-vendor <vendor name> , optional input to specify the vendor name without any space
-lib <library name> , optional input to specify the library name without any space
-version <version> , optional input to specify the version without any space
Returns : Returns the created component object
Example : ipxact_create_component -name i2c [-vendor EU] [-lib mylib] [-version 0.8]
[125] Command : ipxact_component_set_name
Description: Sets name to the given component object or in the currently active component.
Options :
-name <comp name> , mandatory option to specify the component name.
-component <comp object> , optional input to pass the component object whose
name is to be set. If this is not specified then
the given name will be set to the currently active
component.
Returns : Returns the updated component object
Example : ipxact_component_set_name -name foo [-component $comp]
[126] Command : ipxact_create_fileset
Description: Creates FileSet object with the given file name. This object can be added
in the file set list of any component object
Options :
-file <file name> , mandatory option to specify the file name.
Returns : Returns the created fileset object
Example : ipxact_create_fileset -file foo.v
[127] Command : ipxact_component_add_fileset
Description: Adds the given file name in the filesets of the given component object or in
the currently active component.
Options :
-file <foo.v> , mandatory option to specify the file name to be added
-component <component object> , optional input to pass the component object
in which the file to added. In absence of this
input, the file will get added in the fileset of
the currently active component.
Returns : Returns the updated component object after adding the fileset
Example : ipxact_component_add_fileset -file foo.v [-component $comp]
[128] Command : ipxact_component_add_fileset_object
Description: Adds the given file name in the filesets of the given component object or in
the currently active component.
Options :
-fileset <fileSetObj> , mandatory option to specify the fileset object to be added
-component <component object> , optional input to pass the component object
in which the fileset to added. In absence of this
input, the fileset will get added in the currently
active component.
Returns : Returns the updated component object after adding the fileset
Example : ipxact_component_add_fileset -fileset $fileSet [-component $comp]
[129] Command : ipxact_create_bus_def
Description: Creates an IP-XACT Bus Definition with the given details
Options :
-name <BusDef Name > , mandatory option to specify the BusDef name.
-vendor <vendor name> , optional input to specify the vendor name without any space
-lib <library name> , optional input to specify the library name without any space
-version <version> , optional input to specify the version without any space
Returns : Returns the created bus definition object
Example : ipxact_create_bus_def -name clock -[vendor EU] [-lib mylib] [-version 0.8]
[130] Command : ipxact_create_abstraction_def
Description: Creates an IP-XACT Abstraction Definition with the given details
Options :
-name <AbsrtactionDef name> , mandatory option to specify the abstraction
definition name.
-vendor <vendor name> , optional input to specify the vendor name without any space
-lib <library name> , optional input to specify the library name without any space
-version <version> , optional input to specify the version without any space
Returns : Returns the created abstraction definition object
Example : ipxact_create_abstraction_def -name clock [-vendor EU] [-lib mylib] [-version 0.8]
[131] Command : ipxact_create_abstractor
Description: Creates an IP-XACT Abstractor with the given details
Options :
-name <Absrtactor name> , mandatory option to specify the abstractor name.
-vendor <vendor name> , optional input to specify the vendor name without any space
-lib <library name> , optional input to specify the library name without any space
-version <version> , optional input to specify the version without any space
Returns : Returns the created abstractor object
Example : ipxact_create_abstractor -name foo [-vendor EU] [-lib mylib] [-version 0.8]
[132] Command : ipxact_create_design
Description: Creates an IP-XACT Design with the given details
Options :
-vlnv <VLNV> , Optional switch to specify the VLNV i.e.
Vendor,Library,Design Name and Version.
Example, synopsys.com/lib1/DDRPHY/1.5
-name <Name> , Optional switch to specify the design name
Example, DDRPHY
Returns : Returns the created design object
Example : ipxact_create_design -vlnv mycompany/iplib/UART/0.8
ipxact_create_design -name UART
[133] Command : ipxact_design_add_component_instance
Description: Creates a component instance and adds it to the IP-XACT design
Options :
-name <name> , mandatory option to specify the instance name.
-vlnv <VLNV> , mandatory input to specify the component reference
through its VLNV separated with '/'.
Returns : Returns the created component instance object
Example : ipxact_design_add_component_instance -name u_uart -vlnv synopsys/lib/uart/1.3
[134] Command : ipxact_instance_add_configurable_element
Description: Adds specified configurable element i.e. param value to the given component instance.
Options :
-inst <name> , mandatory option to specify the instance name.
-param <param name> , mandatory input to specify the element
to be configured i.e. param value to be overridden
-value <param value> , mandatory input to specify the value
Returns : Returns the created configurable element objec
Example : ipxact_instance_add_configurable_element -inst u_uart -param N -value 20
[135] Command : ipxact_design_add_interface_connection
Description: Adds interface connection between two component instances.
Options :
-name <name> , mandatory option to specify the connection name.
-intf1 <Bus Ref1> , mandatory input to specify the first bus interface , given as compInstName.busRef
-intf2 <Bus Ref2> , mandatory input to specify the second bus interface , given as compInstName.busRef
Returns : Returns the created interface connection object
Example : ipxact_design_add_interface_connection -name conn1 -intf1 comp1.intf1 -intf2 comp2.intf2
[136] Command : ipxact_design_add_adhoc_connection
Description: Adds port-to-port connection between two component instances.
Options :
-name <name> , mandatory option to specify the connection name.
-port1 <inst.port1> , mandatory input to specify the first port
The port can be internal e.g. inst.port1 or
external e.g. topPort ( design's port ).
-port2 <inst2.port2> , mandatory input to specify the second port
The port can be internal e.g. inst.port1 or
external e.g. topPort ( design's port ).
Returns : Returns the created interface connection object
Example : ipxact_design_add_adhoc_connection -name conn1 -port1 comp1.port1 -port2 comp2.port2
[137] Command : ipxact_design_add_adhoc_connection_tied_value
Description: Ties a component instance port with the specified value
Options :
-name <Name> , mandatory option to specify the connection name.
-port <Bus Ref> , mandatory input to specify the component instance port like compInstName.portRef
-value <value> , mandatory input to specify the value to be driven to this component port
Returns : Returns the created interface connection object
Example : ipxact_design_add_adhoc_connection_tied_value -name conn1 -port comp1.port1 -value 0
[138] Command : ipxact_design_save
Description: Saves the given Design object or the currently active design in the
specified file name.
Options :
-xml <file name> , mandatory option to specify the file name to save
-design <design object> , mandatory input to pass the design object
which needs to be saved.
Returns : Returns the same design object after saving the same
Example : ipxact_design_save -xml i2c.design.xml -design $design
[139] Command : ipxact_create_designconfig
Description: Creates an IP-XACT DesignConfig with the given details
Options :
-name <config name> , mandatory option to specify the design config name.
-vendor <vendor name> , optional input to specify the vendor name without any space
-lib <library name> , optional input to specify the library name without any space
-version <version> , optional input to specify the version without any space
Returns : Returns the created designconfig object
Example : ipxact_create_designconfig -name foo [-vendor EU] [-lib mylib] [-version 0.8]
[140] Command : ipxact_create_generator
Description: Creates an IP-XACT Generator with the given details
Options :
-name <generator name> , mandatory option to specify the generator name.
-vendor <vendor name> , optional input to specify the vendor name without any space
-lib <library name> , optional input to specify the library name without any space
-version <version> , optional input to specify the version without any space
Returns : Returns the created generator object
Example : ipxact_create_generator -name myGen [-vendor EU] [-lib mylib] [-version 0.8]
[141] Command : ipxact_load_component_file
Description: Loads an existing IP-XACT component definition file. Make sure that the
name space ( ns ) URI ends with Component. It should be as below-
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/Component .
Options :
-xml <file name> , mandatory option to specify the component file name.
Returns : Returns the loaded component object
Example : ipxact_load_component_file -xml foo.xml
[142] Command : ipxact_component_save
Description: Saves the given component object or the currently active component in the
specified file name.
Options :
-xml <file name> , mandatory option to specify the file name to save
-component <component object> , optional input to pass the component object
which needs to be saved. In absence of this
input, the the currently active component
will get saved in the specified file
Returns : Returns the same component object after saving the same
Example : ipxact_component_save -xml i2c.comp.xml [-component $comp]
[143] Command : ipxact_get_current_component
Description: Returns the currently active component object.
Options :
Returns : Returns the currently active component object
Example : ipxact_get_current_component
[144] Command : ipxact_set_current_component
Description: Sets the given component as currently active component so that
the following/next commands gets executed on this component.
Options :
-component <component object> , mandatory input to pass the component object
to set as the currently active component
Returns : Returns the same component after setting it as the currently active component
Example : ipxact_set_current_component -component $comp
[145] Command : ipxact_get_current_bus_def
Description: Returns the currently active BusDef object
Options :
Returns : Returns the currently active bus definition
Example : ipxact_get_current_bus_def
[146] Command : ipxact_set_current_bus_def
Description: Sets the given busdef as currently active busdef so that
the following/next relevant commands gets executed on this .
Options :
-def <busdef object> , mandatory input to pass the busdef object
to set it as the currently active busdef
Returns : Returns the same bus def after setting that as the currently active bus definition
Example : ipxact_set_current_bus_def -def $bd
[147] Command : ipxact_load_bus_def_file
Description: Loads an existing IP-XACT bus definition file. Make sure that the
name space ( ns ) URI ends with BusDefinition. It should be -
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/BusDefinition .
Options :
-xml <file name> , mandatory option to specify the bus definition file .
Returns : Returns loaded bus definition object
Example : ipxact_load_bus_def_file -xml foo.xml
[148] Command : ipxact_get_current_abstraction_def
Description: Returns the currently active Abstraction Definition object
Options :
Returns : Returns currently active abstraction definition object
Example : ipxact_get_current_abstraction_def
[149] Command : ipxact_set_current_abstraction_def
Description: Sets the given abstraction definition as the currently active abstraction
definition so that the following/next relevant commands gets executed on this .
Options :
-def <abstarct def obj> , mandatory input to pass the abstraction definition object
to set it as the currently active object
Returns : Returns the same abstraction definition object after setting the same as
the currently active abstraction definition
Example : ipxact_set_current_abstraction_def -def $ad
[150] Command : ipxact_load_abstraction_def_file
Description: Loads an existing IP-XACT abstraction definition file. Make sure that the
name space ( ns ) URI ends with AbstractionDefinition. It should be -
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/AbstractionDefinition .
Options :
-xml <file name> , mandatory option to specify the abstraction definition file .
Returns : Returns the loaded abstraction definition object
Example : ipxact_load_abstraction_def_file -xml foo.ad.xml
[151] Command : ipxact_get_current_abstractor
Description: Returns the currently active abstractor object
Options :
Returns : Returns the currently active abstractor object
Example : ipxact_get_current_abstractor
[152] Command : ipxact_set_current_abstractor
Description: Sets the given abstractor object as the currently active abstractor
so that the following/next relevant commands gets executed on this .
Options :
-def <abstarctor obj> , mandatory input to pass the abstractor object
to set it as the currently active abstractor object
Returns : Returns the same abstractor object after setting that as the currently
active abstractor object
Example : ipxact_set_current_abstractor -def $ad
[153] Command : ipxact_get_current_design
Description: Returns the currently active design object
Options :
Returns : Returns the currently active design object
Example : ipxact_get_current_design
[154] Command : ipxact_set_current_design
Description: Sets the given design object as the currently active design
so that the following/next relevant commands gets executed on this .
Options :
-def <design obj> , mandatory input to pass the design object
to set it as the currently active design object
Returns : Returns the same design object after setting that as the currently
active design object
Example : ipxact_set_current_design -def $desObj
[155] Command : ipxact_get_current_designconfig
Description: Returns the currently active designconfig object
Options :
Returns : Returns the currently active designconfig object
Example : ipxact_get_current_designconfig
[156] Command : ipxact_set_current_designconfig
Description: Sets the given designconfig object as the currently active designconfig
so that the following/next relevant commands gets executed on this .
Options :
-def <designconfig obj> , mandatory input to pass the designconfig object
to set it as the currently active designconfig object
Returns : Returns the same designconfig object after setting that as the currently
active designconfig object
Example : ipxact_set_current_designconfig -def $desCfg
[157] Command : ipxact_get_current_generator
Description: Returns the currently active generator object
Options :
Returns : Returns the currently active generator object
Example : ipxact_get_current_generator
[158] Command : ipxact_set_current_generator
Description: Sets the given generator object as the currently active generator
so that the following/next relevant commands gets executed on this .
Options :
-def <generator obj> , mandatory input to pass the generator object
to set it as the currently active generator object
Returns : Returns the same generator object after setting that as the currently
active generator object
Example : ipxact_set_current_generator -def $genObj
[159] Command : ipxact_create_vlnv_library
Description: Returns the LibraryType object by using the given
Vendor, Library, Name and Version details.
Options :
-vendor <vendor name> , mandatory option to provide the
Vendor name without any blank space
-lib <library name> , mandatory option to provide the
library name without any blank space
-name <name> , mandatory option to provide the
object name without any blank space
-version <version> , mandatory option to provide the
version without any blank space
Example : ipxact_create_vlnv_library
[160] Command : ipxact_get_component_factory
Description: Returns the factory to create objects belonging to the component definition
Options :
Example : ipxact_get_component_factory
[161] Command : ipxact_get_bus_def_factory
Description: Returns the factory to create objects belonging to the bus definition
Options :
Example : ipxact_get_bus_def_factory
[162] Command : ipxact_get_abstraction_def_factory
Description: Returns the factory to create objects belonging to the abstraction definition
Options :
Example : ipxact_get_abstraction_def_factory
[163] Command : ipxact_get_abstractor_factory
Description: Returns the factory to create objects belonging to the abstractor
Options :
Example : ipxact_get_abstractor_factory
[164] Command : ipxact_get_design_factory
Description: Returns the factory to create objects belonging to the design
Options :
Example : ipxact_get_design_factory
[165] Command : ipxact_get_generator_factory
Description: Returns the factory to create objects belonging to the generator
Options :
Example : ipxact_get_generator_factory
[166] Command : ipxact_generate_rsa_keys
Description: Generate public and private key files
Options :
-pvtkey <file name>, input to specify the private key file name
-pubkey <file name>, input to specify the public key file name
Example : ipxact_generate_rsa_keys -pvtkey key.pvt.dat -pubkey key.pub.dat
[167] Command : ipxact_preprocess_verilog
Description: Reads the given input file and writes back the preprocessed
output file
Options :
-in <input file name> , mandatory input, to specify the
input file name
-out <ioutput file name> , mandatory input, to specify the
output file name
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-pubkey <public key file> input to pass the public keyfile
with which the data will get decrypted.
This input is mandatory for decryption.
-key <key for encrytption> , input to pass the key with which
the data will get encrypted. This input
is must while encryption and not
required while decrypting an encrypted
file. However, the private is must in
order to decrypt a file.
-pvtkey <private keyfile name> , to specify the name of the
private key file. This input is must
in order to decrypt an encrypted input
file. It is optional when you call this
to encrypt a file. While encryption,
the private key will get dumped in this
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-commented , optional boolean switch to specify if
the 'protect' directives should be inside
the '//' instead of the '`pragma'. By default
its false.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example (for encryption) : ipxact_preprocess_verilog -in foo.v -out processed.v -incdir dir1+dir2 -definedir define+macro1+macro2 -key edautils_dot_com -pubkey pubkey.dat -keyowner SiliconIndia -keyname SI_001
Example(for decryption) : ipxact_preprocess_verilog -in foo.v -out processed.v -incdir dir1+dir2 -definedir define+macro1+macro2 -pvtkey pvtkey.dat -keyowner SiliconIndia -keyname SI_001
[168] Command : ipxact_read_verilog
Description: Reads the given verilog file and converts the specified
top module into IP-XACT component
Options :
-file <file name> , mandatory input, file to be read
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <top name> , input to specify the top module which
needs to be converted into ip-xact
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command ipxact_generate_rsa_keys
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : ipxact_read_verilog -file foo.v -top foo -incdir dir1+dir2 -definedir define+macro1+macro2
[169] Command : ipxact_read_verilog_file_list
Description: Reads the specified multiple verilog files as listed in the input list file
Options :
-file_list <list file> , mandatory input, file where verilog files
are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <top module name>, to provide the top module name
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command ipxact_create_rsa_keys .
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : ipxact_read_verilog_file_list -file_list infile.list -incdir dir1+dir2 -definedir define+macro1+macro2
[170] Command : ipxact_read_verilog_filelist
Description: Reads the specified multiple verilog files as listed in the input list file
Options :
-filelist <list file> , mandatory input, file where verilog files
are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <top module name>, to provide the top module name
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command ipxact_create_rsa_keys .
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : ipxact_read_verilog_filelist -filelist infile.list -incdir dir1+dir2 -definedir define+macro1+macro2
[171] Command : ipxact_import_vhdl
Description: Imports the specified VHDL Entity defined in the given file.
It will convert this entity into a IP-XACT component with same
name and ports and return that component.
Options :
-file <VHDL file> , mandatory option which provides the file where the
entity is defined
-entity <entity name> , mandatory option to provide the entity name to be converted
-work <work lib name> , optional input to specify the work library for analysis
-mapfile <mapfile.ini> , optional input to provide logical to physical library maps
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
Returns : Returns the IP-XACT component object by converting the specified imported VHDL entity
Example : ipxact_import_vhdl -file foo.entity.vhd -entity foo [-work wrk] [-mappfile map.ini]
[172] Command : ipxact_import_mixed_hdl_filelist
Description: Imports the specified multiple Verilog and VHDL files listed in the input list file
Options :
-filelist <list file> , mandatory input, file where VHDL and
Verilog files are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <module to be imported> , mandatory input, top module in this file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
Example : ipxact_import_mixed_hdl_filelist -filelist infile.list -top myTop -incdir dir1+dir2 -definedir define+macro1+macro2
[173] Command : ipxact_find_module
Description: Searches in the database for the given module and return the
verilog module
Options :
-name <module name> , mandatory option to provide the module name
Returns : Returns the verilog module object
Example : ipxact_find_module -name foo
[174] Command : ipxact_find_entity
Description: Searches in the database for the given entity and returns the
entity module
Options :
-name <entity name> , mandatory option to provide the entity name
Returns : Returns the verilog entity object
Example : ipxact_find_entity -name foo
[175] Command : ipxact_create_component_from_module
Description: Converts the given verilog module into IP-XACT component
Options :
-module <module object> , mandatory option to provide the module object
Returns : Returns the IP-XACT component object by converting the specified verilog module object
Example : ipxact_create_component_from_module -module $moduleObject
[176] Command : ipxact_create_module_from_component
Description: Converts the given IP-XACT component into verilog module
Options :
-component <component object> , mandatory option to provide the component object
Returns : Returns the verilog module object by converting the specified IP-XACT component object
Example : ipxact_create_module_from_component -component $compObject
[177] Command : ipxact_create_component_from_entity
Description: Converts the given VHDL entity into an IP-XACT component
Options :
-entity <entity object> , mandatory option to provide the entity object
Returns : Returns the IP-XACT component object by converting the specified VHDL entity object
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
Example : ipxact_create_component_from_entity -entity $entityObject
[178] Command : ipxact_create_entity_from_component
Description: Converts the given IP-XACT component into a VHDL entity
Options :
-component <component object> , mandatory option to provide the component object
Returns : Returns the VHDL entity object by converting the specified IP-XACT component object
Example : ipxact_create_entity_from_component -component $component
[179] Command : ipxact_get_current_bus_interface
Description: Returns the currently active Bus Interface object
Options :
Returns : Returns the currently active bus interface
Example : ipxact_get_current_bus_interface
[180] Command : ipxact_set_current_bus_interface
Description: Sets the given interface as currently active businterface
so that the following/next relevant commands gets executed
on this interface.
Options :
-bif <bus interface object> , mandatory input to pass the
businterface object to set it as the currently
active bus interface
Returns : Returns the same bus interface after setting that as the
currently active bus interface
Example : ipxact_set_current_bus_interface -bif $intf
[181] Command : ipxact_create_slave_bus_interface
Description: Creates bus interface of type slave
Options :
-name <businterface name> , mandatory option to provide the bus interface name
-mem_map_ref < memory map reference > , mandatory input for the memory map reference name
-ad <abstraction definition object> , mandatory input to pass abstraction definition object
-bd <bus definition object> , mandatory input to pass the bus definition object
-bridge_master_interface <bridge master interface > , optional input
-opaque, optional switch to specify if its of type opaque
-conn_required, optional switch to specify if connection required
Returns : Returns the created bus interface object of type slave
Example : ipxact_create_slave_bus_interface -name clk_if -mem_map_ref mmap1 -ad $ad -bd $bd
[182] Command : ipxact_create_master_bus_interface
Description: Creates master type bus interface with the provided details
Options :
-name <businterface name> , mandatory option to provide the bus interface name
-addr_space_ref < reference address space > , mandatory input for address reference
-base_addr <base address>, mandatory input for the base address
-ad <abstraction definition object> , mandatory input to pass abstraction definition object
-bd <bus definition object> , mandatory input to pass the bus definition object
-opaque, optional switch to specify if its of type opaque
-conn_required, optional switch to specify if connection required
Returns : Returns the created bus interface object of type master
Example : ipxact_create_master_bus_interface -name clk_if -addr_space_ref addrref_1 -ad $ad -bd $bd
[183] Command : ipxact_create_misc_bus_interface
Description: Creates bus interface of any type other than master and slave type with the provided details
Options :
-name <businterface name> , mandatory option to provide the bus interface name
-intf_mode <mirrored_master|mirrored_slave|system|monitor> , mandatory input to specify mode
-ad <abstraction definition object> , mandatory input to pass abstraction definition object
-bd <bus definition object> , mandatory input to pass the bus definition object
-opaque, optional switch to specify if its of type opaque
-conn_required, optional switch to specify if connection required
Returns : Returns the created bus interface object of the specified type
Example : ipxact_create_misc_bus_interface -name clk_if -intf_mode mirrored_master -ad $ad -bd $bd -conn_required
[184] Command : ipxact_component_add_bus_interface
Description: Adds the given bus interface to the currently active component or the to component
specified through the -component option
Options :
-bif <businterface object> , mandatory option to provide the bus interface object
-component <component object>, optional switch to specify the component in which
the given bus interface to be added. It will get
added to the currently active component in absence
of this option
Returns : Returns the updated component object
Example : ipxact_component_add_bus_interface -bif $clkIntf [-component $comp]
[185] Command : ipxact_bif_get_abstraction_type
Description: Gets the abstraction type from the given bus interface or from the
currently active bus interface if no bus interface is provided
Options :
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the abstraction type object
Example : ipxact_bif_get_abstraction_type [-bif $clockIntf]
[186] Command : ipxact_bif_get_any_attribute
Description: Gets the AnyAttribute type from the given bus interface or from the
currently active bus interface if no bus interface is provided
Options :
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the any attribute type
Example : ipxact_bif_get_any_attribute [-bif $clockIntf]
[187] Command : ipxact_bif_get_bits_in_lau
Description: Gets the bits in lau in the given bus interface or in the
currently active bus interface
Options :
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the bits in lau
Example : ipxact_bif_get_bits_in_lau [-bif $clockIntf]
[188] Command : ipxact_bif_get_bit_steering
Description: Gets the bit steering in the given bus interface or in the
currently active bus interface
Options :
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the bitsteering
Example : ipxact_bif_get_bit_steering [-bif $clockIntf]
[189] Command : ipxact_bif_get_parameters
Description: Gets the parameters in the given bus interface or in the
currently active bus interface
Options :
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the parameters
Example : ipxact_bif_get_parameters [-bif $clockIntf]
[190] Command : ipxact_bif_get_port_maps
Description: Gets the port maps in the given bus interface or in the
currently active bus interface
Options :
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the portmaps
Example : ipxact_bif_get_port_maps [-bif $clockIntf]
[191] Command : ipxact_bif_set_abstraction_def
Description: Sets the given abstraction definition to the given bus interface
or in the currently active bus interface
Options :
-ad <abs def object> , mandatory input to specify the abstraction definition object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_get_port_maps -ad $adObj [-bif $clockIntf]
Where the $adObj gets created by loading an abstraction definition XML file
[192] Command : ipxact_bif_set_bus_def
Description: Sets the given bus definition object in the given bus interface
or in the currently active bus interface
Options :
-bd <bus def object> , mandatory input to specify the bus definition object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_bus_def -bd $bdObj [-bif $clockIntf]
Where the $bdObj gets created by loading a bus definition XML file
[193] Command : ipxact_bif_set_name
Description: Sets the name to the given bus interface or to the currently active bus interface
Options :
-name <bif name> , mandatory input to specify the name to be set to the bus interface
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_bus_def -name foo [-bif $clockIntf]
[194] Command : ipxact_create_logical_port
Description: Creates a logical port with the given details required to create
port map in the bus interface
Options :
-name < name of port > , mandatory input to specify the name of the port
-left <left of range> , optional input to specify the left bound of range if
this port is a vector port
-right <right of range>, optional input to specify the right bound of range if
this port is a vector port
Returns : Returns the created logical port
Example : ipxact_create_logical_port -name data -left 31 -right 0
ipxact_create_logical_port -name clock
[195] Command : ipxact_create_physical_port
Description: Creates a physical port with the given details required to create
port map in the bus interface
Options :
-name < name of port > , mandatory input to specify the name of the port
-left <left of range> , optional input to specify the left bound of range if
this port is a vector port
-right <right of range>, optional input to specify the right bound of range if
this port is a vector port
Returns : Returns the created physical port
Example : ipxact_create_physical_port -name data -left 31 -right 0
ipxact_create_physical_port -name clk
[196] Command : ipxact_create_portmap
Description: Creates port map with the given logical and physical ports. This port map object
cab added in the port map list of a given bus interface.
Options :
-logical <logical port object> , mandatory input to specify the logical port
-physical <physical port object> , mandatory input to specify the physical port
Returns : Returns the port map object
Example : ipxact_create_portmap -logical clock -physical CLK
[197] Command : ipxact_bif_add_port_map
Description: Adds the given port map in the port map list of the given bus interface or
or the currently active bus interface
Options :
-pmap <port map object> , mandatory input to specify the port map to be added
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_add_port_map -pmap $myclkmap
[198] Command : ipxact_bif_set_master
Description: Sets the given master object in the given bus interface
Options :
-master <master object> , mandatory input to specify the master object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_master -master <master object>
[199] Command : ipxact_bif_set_slave
Description: Sets the given slave object in the given bus interface
Options :
-slave <slave object> , mandatory input to specify the slave object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_slave -slave <slave object>
[200] Command : ipxact_bif_set_system
Description: Sets the given system object in the given bus interface
Options :
-system <system object> , mandatory input to specify the system object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_system -system <system object>
[201] Command : ipxact_bif_set_monitor
Description: Sets the given monitor object in the given bus interface
Options :
-monitor <monitor object> , mandatory input to specify the monitor object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_monitor -monitor <monitor object>
[202] Command : ipxact_bif_set_mirrored_master
Description: Sets the given mirrored master object in the given bus interface
Options :
-master <mirrored master object> , mandatory input to specify the mirrored master object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_mirrored_master -master <mirrored master object>
[203] Command : ipxact_bif_set_mirrored_slave
Description: Sets the given mirrored slave object in the given bus interface
Options :
-slave <mirrored slave object> , mandatory input to specify the mirrored slave object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_mirrored_slave -slave <mirrored slave object>
[204] Command : ipxact_bif_set_mirrored_system
Description: Sets the given mirrored system object in the given bus interface
Options :
-system <mirrored system object> , mandatory input to specify the mirrored system object
-bif <businterface object> , optional input to provide the bus interface object.
The currently active bus interface will be used in
absence of this option.
Returns : Returns the updated bus interface object
Example : ipxact_bif_set_mirrored_system -system <system object>
[205] Command : ipxact_bif_create_master
Description: Creates Master type object with the given base address
Options :
-base_addr <base address> , mandatory input to specify the base address
Returns : Returns the master object created by this
Example : ipxact_bif_create_master -base_addr $baseAddr
[206] Command : ipxact_create_memory_map
Description: Creates a memory map object with the given name and other optional details
Options :
-name <mmap name> , mandatory option to provide the memory map name
-base_address <base address> , optional input to provide the base address
-bank_alignment_name <bank alignment name> , optional input to provide the bank alignment name
-bank_alignment_type <parallel|serial> , optional input to provide the bank alignment type
-addr_blk_name <addr block name> , optional input to provide the address block name
-addr_blk_range <addr block range> , optional input to provide the address block range
-addr_blk_width <block width> , optional input to provide the address block width
-addr_bit_units <address bit ubits> , optional input to provide the address bit units
-usage_type <memory|register|reserved> , optional input to define the usage type
-access_type <read_only|read_write|read_write_once|write_once|write_only> , optional input
-is_volatile , optional boolean switch to specify if its volatile
Returns : Returns the memory map object
Example : ipxact_create_memory_map -name mmap_1 [-base_address <base address>]
[-bank_alignment_name <bank alignment name>]
[-bank_alignment_type <parallel|serial>]
[-addr_blk_name <name od address block>]
[-addr_blk_range <address block range>]
[-addr_blk_width <block width>]
[-addr_bit_units <address bit ubits>]
[-usage_type <memory|register|reserved>]
[-access_type <read_only|read_write|read_write_once|write_once|write_only>]
[-is_volatile]
[207] Command : ipxact_component_add_memory_map
Description: Adds the given memory map object to the given component object or
to the currently active component.
Options :
-mmap <memory map object> , mandatory option to specify memory map object
-component <comp object> , optional input to pass the component where this
mmap is to be added. If this is not specified then
the given mmap will be added to the currently active
component.
Returns : Returns updated component object
Example : ipxact_component_add_memory_map -mmap $mmap1 [-component $comp]
[208] Command : ipxact_create_register
Description: Creates register object with the given name and other optional details
Options :
-name <name of the register> , mandatory input to specify the register name
-offset <offset address> , optional input to specify the offset address
-size <size in integer> , optional input to specify the size of the register
-access_type <read_only|read_write|read_write_once|write_once|write_only> , optional input
-reset_val <reset value> , optional input to specify the reset value
-reset_mask <value of reset mask> , optional input to specify reset mask value
-is_volatile , optional boolean switch to specify if its volatile
Returns : Returns the register object created by this
Example : ipxact_create_register -name CTRL_REG -offset 0x1000 -size 32 -access_type read_write -reset_val 0x00000000 -reset_mask 0x00000fff -is_volatile
[209] Command : ipxact_memory_map_add_register
Description: Adds the given register object to the specified memory map object or
to the currently active memory map.
Options :
-register <register object> , mandatory option to specify memory map object
-mmap <mmap object> , optional input to pass the memory map object where this
register has to be added.
Returns : Returns updated memory map object
Example : ipxact_memory_map_add_register -register $reg1 [-mmap $mmap1]
[210] Command : ipxact_create_bit_field
Description: Creates bitfield object with the given name and other optional details
Options :
-name <name of the bitfield> , mandatory input to specify the bitfield name
-offset <bit offset> , optional input to specify the offset bit
-width <width in integer> , optional input to specify the width of this bitfield
-access_type <read_only|read_write|read_write_once|write_once|write_only> , optional input
Returns : Returns the bitfield object created by this
Example : ipxact_create_register -name CTRL_REG -offset 3 -width 2 -access_type read_write
[211] Command : ipxact_register_add_bit_field
Description: Adds the given bitfield object to the specified register object or
to the currently active register.
Options :
-bit_field <bitfield object> , mandatory option to specify bitfield object
-register <register object> , optional input to pass the register object
where this register to be added.
Returns : Returns updated register object
Example : ipxact_register_add_bit_field -bit_field $field1 [-register $reg1]
[212] Command : rtlutils_generate_rsa_keys
Description: Generate public and private key files
Options :
-pvtkey <file name>, input to specify the private key file name
-pubkey <file name>, input to specify the public key file name
Example : rtlutils_generate_rsa_keys -pvtkey key.pvt.dat -pubkey key.pub.dat
[213] Command : rtlutils_preprocess_verilog
Description: Reads the given input file and writes back the preprocessed
output file
Options :
-in <input file name> , mandatory input, to specify the
input file name
-out <ioutput file name> , mandatory input, to specify the
output file name
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-pubkey <public key file> input to pass the public keyfile
with which the data will get decrypted.
This input is mandatory for decryption.
-key <key for encrytption> , input to pass the key with which
the data will get encrypted. This input
is must while encryption and not
required while decrypting an encrypted
file. However, the private is must in
order to decrypt a file.
-pvtkey <private keyfile name> , to specify the name of the
private key file. This input is must
in order to decrypt an encrypted input
file. It is optional when you call this
to encrypt a file. While encryption,
the private key will get dumped in this
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-commented , optional boolean switch to specify if
the 'protect' directives should be inside
the '//' instead of the '`pragma'. By default
its false.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example (for encryption) : rtlutils_preprocess_verilog -in foo.v -out processed.v -incdir dir1+dir2 -definedir define+macro1+macro2 -key edautils_dot_com -pubkey pubkey.dat -keyowner SiliconIndia -keyname SI_001
Example(for decryption) : rtlutils_preprocess_verilog -in foo.v -out processed.v -incdir dir1+dir2 -definedir define+macro1+macro2 -pvtkey pvtkey.dat -keyowner SiliconIndia -keyname SI_001
[214] Command : rtlutils_read_verilog
Description: Reads the specified verilog file so that the module can be instantiated.
Options :
-file <file name> , mandatory input, file to be read
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command rtlutils_generate_rsa_keys
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : rtlutils_read_verilog -file foo.v -incdir dir1+dir2 -definedir define+macro1+macro2
[215] Command : rtlutils_read_verilog_filelist
Description: Reads the specified multiple verilog files listed in the input file
Options :
-filelist <list file> , mandatory input, file where verilog files
are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command rtlutils_create_rsa_keys .
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : rtlutils_read_verilog_filelist -filelist infile.list -incdir dir1+dir2 -definedir define+macro1+macro2
[216] Command : rtlutils_read_verilog_file_list
Description: Reads the specified multiple verilog files listed in the input file
Options :
-file_list <list file> , mandatory input, file where verilog files
are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
-key <key for encrytption> , mandatory input while encrypting
-pvtkey <private keyfile name> , mandatory input while
while encrypting an input file. This
file can be created if does not exists
with the command rtlutils_create_rsa_keys .
-pubkey <public keyfile name> , to specify the name of the
public key file. This input is must
in order to decrypt an encrypted input
file.
-keyowner <Owner of the key> , Optional input to specify
the name of the key owner. Generally,
name of the company is specified here.
-keyname <name of the key> , Optional input to specify
the name of the key.
-algo <algo name> , optional input, to pass the name of the
algorithm which will be used to decrypt
the protected functionality. Default is
value AES.
Example : rtlutils_read_verilog_file_list -file_list infile.list -incdir dir1+dir2 -definedir define+macro1+macro2
[217] Command : rtlutils_read_vhdl_filelist
Description: Reads/parses the given VHDL file list as specified in
the commandline through the option -filelist .
Options :
-filelist <infile.list> , mandatory option to specify the
input file which contains VHDL files
-work <library name> , optional input to specify the library
where this file needs to be compiled.
Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the updated VHDL design root of type 'FVhPRoot'
Example : rtlutils_read_vhdl_filelist -filelist foo.vhd [-work WORK] [-mapfile map.ini ]
[218] Command : rtlutils_read_vhdl
Description: Reads/parses the given VHDL file as specified in
the commandline through the option -file .
Options :
-file <VHDL file > , mandatory option to specify the input
VHDL file
-work <library name> , optional input to specify the library
where this file needs to be compiled.
Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the updated VHDL design root of type 'FVhPRoot'
Example : rtlutils_read_vhdl -file foo.vhd [-work WORK] [-mapfile map.ini ]
[219] Command : rtlutils_import_mixed_hdl_filelist
Description: Imports the specified multiple Verilog and VHDL files listed in the input list file
Options :
-filelist <list file> , mandatory input, file where VHDL and
Verilog files are listed
-excludefilelist <exclude.list> , optional input to exclude
files listed in the given file
-top <module to be imported> , mandatory input, top module in this file
-incdir <directories> , optional input, directories where include
files to be searched
-definedir <macros to be defined> , optional input, directives to
be defined
-nowildcard , optional boolean switch to disable wildcard processing in file name(s)
Example : rtlutils_import_mixed_hdl_filelist -filelist infile.list -top myTop -incdir dir1+dir2 -definedir define+macro1+macro2
[220] Command : rtlutils_vhdl_find_entity
Description: Returns the VHDL entity with the specified name
Options :
-name <entity name> , mandatory option to specify the entity
name to be loaded
-work <library name> , optional input to specify the library
from where this entity needs to be
loaded. Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the VHDL entity object
Example : rtlutils_vhdl_find_entity -name foo [-work WORK] [-mapfile map.ini ]
[221] Command : rtlutils_vhdl_find_architecture
Description: loads the specified architecture of a given entity
Options :
-name <arch name> , optional input to specify the
architecture name to be loaded. If not
specified then the most recently compiled
architecture will get loaded
-entity <entity name> , mandatory input to specify the entity
name whose architecture to be loaded
-work <library name> , optional input to specify the library
from where this architecture/entity
needs to be loaded. Default library
is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the architecture object corresponding to
the specified entity
Example : rtlutils_vhdl_find_architecture [-name arch1] -entity foo [-work WORK] [-mapfile map.ini ]
[222] Command : rtlutils_vhdl_find_configuration
Description: Returns the VHDL configuration with the specified name
Options :
-name <config name> , mandatory option to specify the name
of the configuration to be loaded
-work <library name> , optional input to specify the library
from where this configuration needs
to be loaded. Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the VHDL configuration object
Example : rtlutils_vhdl_find_configuration -name myConfig1 [-work WORK] [-mapfile map.ini ]
[223] Command : rtlutils_vhdl_find_package
Description: loads the specified package from the given library or
from the 'work' library
Options :
-name <pack name> , mandatory input to specify the
package name to be loaded.
-work <library name> , optional input to specify the library
from where this package to be loaded.
Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the package object
Example : rtlutils_vhdl_find_package -name mypack [-work WORK] [-mapfile map.ini ]
[224] Command : rtlutils_vhdl_find_package_body
Description: loads the specified package body from the given library or
from the 'work' library
Options :
-name <pack name> , mandatory input to specify the
package name whose body to be loaded.
-work <library name> , optional input to specify the library
from where this package to be loaded.
Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : Returns the package object
Example : rtlutils_vhdl_find_package_body -name mypack [-work WORK] [-mapfile map.ini ]
[225] Command : rtlutils_generate_vhdl_testbench
Description: Generates VHDL testbench from the given entity object.
Options :
-entity <entity object> , mandatory input to specify the
entity object whose testbench
has to be created.
-outfile <output file name> , optional input to specify the
output testbench file name
Returns : The entity which was passed as argument
Example : rtlutils_generate_vhdl_testbench -entity top [-outfile tb.vhd]
[226] Command : rtlutils_create_module_from_entity
Description: Converts an entity into Verilog module ( just ports & params )
Options :
-entity <entity object> , mandatory input to specify the
entity object which needs to be
converted into Verilog module
Returns : Verilog Module Object translated from the entity
Example : rtlutils_create_module_from_entity -entity top
[227] Command : rtlutils_generate_verilog_testbench
Description: Generates Verilog testbench from the given verilog
module object.
Options :
-module <module object> , mandatory input to specify the
module object whose testbench
has to be created.
-outfile <output file name> , optional input to specify the
output testbench file name
Returns : The module which was passed as argument
Example : rtlutils_generate_verilog_testbench -module top [-outfile tb.v]
[228] Command : rtlutils_translate_verilog_module_into_systemc
Description: Converts a verilog module into equivalent SystemC . It also
generates drivers. monitors and Makefiles optionally.
Options :
-module <module object> , mandatory input to specify the
module object which needs to be
converted into SystemC
-outdir <output dir name> , optional input to specify the
directory name in which the SystemC
class and header files will get
generated
-two_value_logic , optional switch to specify of the SystemC
ports/variables need to be of two value
logic ( '0' and '1' ) instead of the default
four value logic( '0', '1', 'x', 'z' )
-write_driver_monitor , optional switch to specify if the
driver and monitors need to be
generated
Returns : The module which was passed as argument
Example : rtlutils_translate_verilog_module_into_systemc -module $modObj [-outdir sc_dir] [-two_value_logic] [-write_driver_monitor]
[229] Command : rtlutils_link_verilog_module
Description: Links the specified verilog module object by connecting
all the instances in the entire hierarchy. Will search
replace all undefined modules with their definition
to ensure that there is no undefined module .
Options :
-module <module object> , mandatory input to specify the
module object which needs to be
linked
Returns : The module after linking it
Example : rtlutils_link_verilog_module -module $modObj
[230] Command : rtlutils_elaborate_verilog_module
Description: Elaborates the specified verilog module
Options :
-module <module object> , mandatory input to specify the
module object which needs to be
elaborated
Returns : The module after elaborating it
Example : rtlutils_elaborate_verilog_module -module $modObj
[231] Command : rtlutils_verilog_create_hierarchy
Description: Inserts a new hierarchy with the specified name by
grouping the list of instances in the given module object
Options :
-module <module object> , mandatory input to specify the
module object whose instances to
be put together in a new hierarchy.
Example - -module $myMod
-colon_separated_inst_names <name of instances to be grouped> ,
Mandatory input to provide the list of
instances which needs to be grouped.
Example- inst1:inst2 where 'inst1' and
'inst2' are the instances inside the
module which has been passed with the
-module option.
-new_hierarchy_name <new inst name> , mandatory input to
specify the name of the new instance
enclosing the list of the instances.
Example: -new_hierarchy_name newInst
-enclosing_module_name <new mod name> , mandatory input to
specify the name of the module inside
which the given list of instances will
be put together.
Example: -enclosing_module_name newMod
Returns : The module object after inserting the hierarchy i.e. after
grouping the instances
Example : rtlutils_verilog_create_hierarchy -module $myMod -colon_separated_inst_names inst1:inst2 -new_hierarchy_name newInst -enclosing_module_name newMod
The above command creates a new module named 'newMod' and
places the instances 'inst1' and 'inst2' inside this new
module 'newMod' by removing the same from the given '$myMod'
module object . This module 'newMod' gets instantiated in
the '$myMod' . This is how the new hierarchy gets inserted.
[232] Command : rtlutils_verilog_module_find_nets
Description: Searches in the given module for the nets matching with the
given net name( can be tcl pattern as well ).
Options :
-module <module object> , mandatory input to specify the
module object where the net(s)
need t be searched
-name </mynet*> , mandatory input to provide the net name or
a pattern for the net name
-hier , optional input to specify if the entire hierarchy needs
to be searched.
Returns : The list of nets matching with the names
Example : rtlutils_verilog_module_find_nets -module $myMod -name </mynet*> [-hier]
[233] Command : rtlutils_verilog_module_find_ports
Description: Searches in the given module for the ports matching with the
given port name( can be tcl pattern as well ).
Options :
-module <module object> , mandatory input to specify the
module object where the port(s)
need t be searched
-name </in*> , mandatory input to provide the port name or
a pattern for the port name
-hier , optional input to specify if the entire hierarchy needs
to be searched.
Returns : The list of ports matching with the names
Example : rtlutils_verilog_module_find_ports -module $myMod -name </inp*> [-hier]
[234] Command : rtlutils_verilog_module_find_instances
Description: Searches in the given module for the instances matching
with the given name( accepts regular expression as name )
Options :
-module <module object> , mandatory input to specify the
module object where the port(s)
need t be searched
-name </in*> , mandatory input to provide the instance name or
a regexpr for the instance name
-hier , optional input to specify if the entire hierarchy needs
to be searched.
Returns : The list of instances matching with the given name
Example : rtlutils_verilog_module_find_instances -module $myMod -name </inp*> [-hier]
[235] Command : rtlutils_verilog_module_find_instances_of_module
Description: Searches in the given root module and its entire hierarchy
to list down all the instances of a given module.
Options :
-module_name <module name> , mandatory input to specify the
name of the module whose instances to be searched.
-root_module <root module object> , the root module where from
the search should start
-inst_name <instance name pattern> , mandatory input to specify
instance name/pattern to filter the instances
-hier , optional input to specify if the entire hierarchy
needs to be searched.
Returns : The list of instances
Example : rtlutils_verilog_module_find_instances_of_module -module_name midMod -root_module $topMod -inst_name .* -hier
[236] Command : rtlutils_verilog_module_find_gate_instances
Description: Searches in the given module and its entire hierarchy in the
hierarchical mode to list down all the gates/primitive
instances
Options :
-module <module obj> , mandatory input to specify the
module object in where to search for the
primitive gate instances
-name <instance name pattern> , mandatory input to specify
instance name pattern to filter out the instances
matching with this pattern
-hier , optional input to specify if the entire hierarchy
needs to be searched.
Returns : The list of instances
Example : rtlutils_verilog_module_find_gate_instances -module $myMod -name .* [-hier]
[237] Command : rtlutils_verilog_module_find_udp_instances
Description: Searches in the given module and its entire hierarchy in the
hierarchical mode to list down all the udp instances
Options :
-module <module obj> , mandatory input to specify the
module object in where to search for the
udp instances
-name <instance name pattern> , mandatory input to specify
instance name pattern to filter out the instances
matching with this pattern
-hier , optional input to specify if the entire hierarchy
needs to be searched.
Returns : The list of instances
Example : rtlutils_verilog_module_find_udp_instances -module $myMod -name .* [-hier]
[238] Command : rtlutils_verilog_find_module
Description: Searches for the specified in the design database
Options :
-name <module name> , mandatory input to specify the
module name which needs to be searched in the
design database
Returns : The module object matching with the name
Example : rtlutils_verilog_find_module -name foo
[239] Command : rtlutils_verilog_find_modules
Description: Searches for the modules matching with the regular
expression
Options :
-name <regexpr> , mandatory input to specify the
module name as regular expression which
needs to be searched in the design database
Returns : The list module objects matching with the name
Example : rtlutils_verilog_find_modules -name /myM*
[240] Command : rtlutils_verilog_module_flatten
Description: Flattens a verilog module object as passed as argument
Options :
-module <module object> , mandatory input to specify the
input module which needs to be flattened.
-delimeter <hierarchy delimeter character> , optional input
to specify the hierarchy delimeter
-all_hier , optional input to specify if the entire needs to
flattened
-stop_at_leaf , optional input to stop the flattening of the
leaf level modules.
-disable_assignment_merge , optional input to disable the
the assignment merging which is true by default.
-flatten_undefined_modules , optional input to specify if the
undefined modules needs to flattened
-remove_unused_nets , optional input switch to specify
if unused nets to be removed
-rename_nets , optional switch to specify the nets to be
renamed to reduce the net name string.
Returns : The same input module after flattening it as per the doc
Example : rtlutils_verilog_module_flatten -module $myMod -delimeter "." [-all_hier] [-stop_at_leaf] [-disable_assignment_merge] [-flatten_undefined_modules] [-remove_unused_nets] [-rename_nets]
[241] Command : rtlutils_verilog_module_remove_concurrent_assignments
Description: Removes the given concurrent assignments statement from
the given module
Options :
-module <module object> , mandatory input to specify the
input module module from which the assignments
needs to be removed.
Returns : The same input module after removing the assignments
Example : rtlutils_verilog_module_remove_concurrent_assignments -module $modObj
[242] Command : rtlutils_verilog_module_remove_hierarchy
Description: Removes the given concurrent assignments statement from
the given module
Options :
-module <module object> , mandatory input to specify the
input module module from which the assignments
needs to be removed.
-delimeter <hierarchy delimeter character> , optional input
to specify the hierarchy delimeter
-all_hier , optional input to specify if the entire needs to
flattened
-stop_at_leaf , optional input to stop the flattening of the
leaf level modules.
Returns : The same input module after flattening it
Example : rtlutils_verilog_module_remove_hierarchy -module $modObj [-delimeter "."] [-all_hier] [-stop_at_leaf]
[243] Command : rtlutils_print_clock_reset_tree
Description: Prints the list of clock/reset tree starting from the
given clock/reset netname in the specified module until
it hits the given endpoint. The endpoints are nothing
but the list of library cells which are not part of the
clock/reset tree path.
Options :
-module <module name>, mandatory input to specify the module
name from where the clock tree starts
-from <clock or reset name>, mandatory input to specify the
root clock or reset name from where
path needs to be traced.
-to <ff:or:decoder> , mandatory input to provide the list
of library cells separated with
colon(:) which are not part of the
clock/reset tree. This input is
required in order to find the end of
of the tree path. Generally it will
be flip-flops ...
-buffers <ctb:mux:icg> , mandatory input to provide the
list of library cells separated with
colon(:) which are part of the
clock/reset tree. The clock/reset
buffers, ICG and some mux may be
part of this argument.
-nonets , optional input to specify if the intermediate
nets to be ignored. Default, its false
-noformat , optional input to stop formatting of the output
-exact , optional input to specify if the given clock/reset
names are exact full names i.e. skip
pattern matching in clock/rst names
Returns : The list of clock/reset tree paths. Prints the same.
Example : rtlutils_print_clock_reset_tree -module top_module -from clk -to ff1:ff2 -buffers ctb:icg1:mux2 -nonets
[244] Command : rtlutils_create_wrapper_verilog_in_verilog
Description: Creates a Verilog wrapper module by instantiating the specified
module.
Options :
-module <module name>, mandatory input to specify the module
name around which the wrapper needs to
be generated.
-flatten , optional boolean switch to enable the splitting of
the multidimensional port arrays
-wrapper <module name> optional switch to specify the name
of the wrapper module to be created.
-outfile <file name> optional switch to specify the name
of the output file where the wrapper module will
be written
Returns : The wrapper module object
Example : rtlutils_create_wrapper_verilog_in_verilog -module originalModule -wrapper wrapperModule -flatten -outfile wrapperModule.sv
[245] Command : rtlutils_create_wrapper_vhdl_in_vhdl
Description: Creates a VHDL wrapper module by instantiating the specified
entity.
Options :
-entity <entity name>, mandatory input to specify the entity
name around which the wrapper needs to
be generated.
-wrapper <entity name> optional switch to specify the name
of the wrapper entity to be created.
-outfile <file name> optional switch to specify the name of the output file where the
wrapper entity and architecture will be written
-work <library name> , optional input to specify the library
from where this entity to be loaded.
Default library is 'work'
-mapfile <library mapfile> , optional input to specify the
logical to physical library map
Returns : The wrapper entity object
Example : rtlutils_create_wrapper_vhdl_in_vhdl -entity originalEntity -wrapper wrapperEntity -outfile wrapper.vhd
[246] Command : rtlutils_clean_vhdl_design_database
Description: Cleans up the internal design database for fresh parsing of
vhdl design units. This is would be required when comparing
two entities with same name. You should parse the files
containing the golden entity/arch and then clean up the
design database to avoid the multiple definition error and
then parse the revised RTL file(s) containing the modified
definition of the same entity/arch.
Options : None
Returns : None
Example : rtlutils_clean_vhdl_design_database
[247] Command : rtlutils_clean_verilog_design_database
Description: Cleans up the internal design database for fresh parsing of
modules. This is would be required when comparing two modules
with same name. You should parse the files containing the
golden module and then clean up the design database to avoid
the multiple definition error and then parse the revised RTL
file(s) containing the modified definition of the same module.
Options : None
Returns : None
Example : rtlutils_clean_verilog_design_database
[248] Command : rtlutils_find_verilog_module
Description: Searches for the modules matching with the regular
expression
Options :
-name <module name> , mandatory input to specify the
module name which needs to be searched in the
design database
Returns : The module object matching with the name
Example : rtlutils_find_verilog_module -name foo
[249] Command : rtlutils_compare_verilog_modules
Description: Compare two verilog module's parameter's, ports, interfaces and instances
Options :
-golden <golden module name>, mandatory input to specify the golden
module name. You must invoke the command
rtlutils_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-revised <revised module name>, mandatory input to specify the revised
module name. You must invoke the command
rtlutils_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-ignore_insts , optional boolean switch to ignore comparsion of instanc(s), use this switch
if you want to compare only the ports and parameters
-ignore_assgns , optional boolean switch to ignore comparsion of concurrent statements, use this switch
if you want to compare only the ports and parameters
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : rtlutils_compare_verilog_modules -golden mod_gld -revised mod_rev -outcsv foo.csv -outtxt bar.txt
[250] Command : rtlutils_compare_verilog_module_objects
Description: Compare two verilog module's parameter's, ports, interfaces and instances
Options :
-golden <golden module object>, mandatory input to specify the golden
module object. You must invoke the command
rtlutils_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-revised <revised module object>, mandatory input to specify the revised
module object. You must invoke the command
rtlutils_clean_verilog_design_database in between reading
the golden and the revised Verilog files
-ignore_insts , optional boolean switch to ignore comparsion of instanc(s), use this switch
if you want to compare only the ports and parameters
-ignore_assgns , optional boolean switch to ignore comparsion of concurrent statements, use this switch
if you want to compare only the ports and parameters
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : rtlutils_compare_verilog_module_objects -golden mod_gld -revised mod_rev -outcsv foo.csv -outtxt bar.txt
[251] Command : rtlutils_clean_vhdl_design_database
Description: Cleans up the internal design database for fresh parsing of
vhdl design units. This is would be required when comparing
two entities with same name. You should parse the files
containing the golden entity/arch and then clean up the
design database to avoid the multiple definition error and
then parse the revised RTL file(s) containing the modified
definition of the same entity/arch.
Options : None
Returns : None
Example : rtlutils_clean_vhdl_design_database
[252] Command : rtlutils_compare_vhdl_entities
Description: Compare two vhdl entity's generics, ports and instances in the
architectures( most recently compiled architecture )
Options :
-golden <golden entity name>, mandatory input to specify the golden
entity name. You must invoke the command
rtlutils_clean_vhdl_design_database in between reading
the golden and the revised VHDL files.
You should compile the golden RTLs in golden library
and revised RTLs in the revised library if the entity
names are same
-revised <revised entity name>, mandatory input to specify the revised
entity name. You must invoke the command
rtlutils_clean_vhdl_design_database in between reading
the golden and the revised Verilog files
Note: You should compile the golden RTLs in golden library
and revised RTLs in the revised library if the entity
names are same
-golden_work <golden work library name>, mandatory input to specify the golden work( logical )
library name. Make sure that this library was used with
the -work switch while reading/analyzing/importing the RTLs
containing the golden entity/arch. Also ensure that your
specified library exists in the mapfile passed through the -mapfile switch
-revised_work <revised work library name>, mandatory input to specify the revised work( logical )
library name. Make sure that this library was used with
the -work switch while reading/analyzing/importing the RTLs
containing the revised entity/arch. Also ensure that your
specified library exists in the mapfile passed through the -mapfile switch
-mapfile <mapfile name>, mandatory input to specify the VHDL library mappings.
This map file needs to be created by the user thought any text editor.
Each line should contain one library mapping, example-
revised_wrk=/user/klg/vhdl/work/revised
golden_wrk=/user/klg/vhdl/work/golden
If your mapfile contains above two lines, then you can specify
revised_wrk for the -revised_work and golden_wrk for the -golden_work
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : rtlutils_compare_vhdl_entities -golden gld_entity -revised modified_ent -golden_work work1 -revised_work work2 -mapfile mapfile.ini -outcsv diff.csv -outtxt diff.txt
[253] Command : rtlutils_compare_vhdl_entity_objects
Description: Compare two VHDL entity objects- ports, interfaces and instances
Options :
-golden <golden entity object>, mandatory input to specify the golden
entity object. You must invoke the command
rtlutils_clean_vhdl_design_database in between reading
the golden and the revised VHDL files
-revised <revised entity object>, mandatory input to specify the revised
entity object. You must invoke the command
rtlutils_clean_vhdl_design_database in between reading
the golden and the revised VHDL files
-outcsv <output CSV file name>, optional input to specify the file name
where the diffs will be printed as CSV/XLS.
Default file name is diff.csv
-outtxt <output Text file name>, optional input to specify the file name
where the diffs will be printed in text format
Default file name is diff.txt
Returns : None
Example : rtlutils_compare_vhdl_entity_objects -golden gld_ent -revised rev_ent -outcsv foo.csv -outtxt bar.txt
[254] Command : replace_variables
[255] Command : enable_debug
[256] Command : disable_debug
[257] Command : upf_comapre
Description: Compares two UPF files and reports the differences.
Options :
-rev <upf.modified.tcl>, mandatory option to specify the modified UPF file
-gld <upf.original.tcl>, mandatory option to specify the original UPF file
Example : upf_comapre -rev upf.modified.tcl -gld upf.original.tcl
[258] Command : upf_set_search_paths
Description: Sets search paths , used while loading upf file
Options :
Example : upf_set_search_paths { path1 path2 path3 }
[259] Command : upf_version
Description: Sets upf version
Options :
Example : upf_version 3.0
[260] Command : set_design_top
Description: Sets top design
Options :
Example : set_design_top ALU07
[261] Command : set_scope
Description: Sets UPF command scope
Options :
Example : set_scope /top/dut_i
[262] Command : findElement
[263] Command : load_upf
Description: Loads an existing UPF File
Options :
Example : load_upf foo.upf
[264] Command : load_upf_protected
Description: Loads an existing UPF File
Options : load_upf_protected upf_ file_name [-hide_globals] [-scope instance_name_list] [-params param_list]
Example : load_upf_protected foo.upf
[265] Command : create_power_domain
Description: Creates power domain
Options :
Example : create_power_domain PD1 -elements my_inst_1
create_power_domain PD1 elements { my_inst_1 hier1/subhier1 }
[266] Command : create_composite_domain
Description: Creates composite domain
Options :
Example : create_composite_domain my_combo_domain_name
-subdomains {a/pd1 b/pd2}
-supply {primary could_be_on_ss}
[267] Command : create_supply_set
Description: Creates supply set
Options :
Example : create_supply_set relative_always_on_ss -function {power vdd} -function {ground vss}
create_supply_set relative_always_on_ss -update -reference_gnd {earth_ground}
create_supply_set PD1.primary -update -function {nwell bias}
[268] Command : create_supply_net
Description: Creates supply net
Options :
Example : create_supply_net local_vdd_3 -resolve one_hot
[269] Command : create_logic_net
Description: Creates logic net
Options :
Example : create_logic_net local_vdd_3 -resolve one_hot
[270] Command : set_domain_supply_net
Description: set domain supply net
Options :
Example : set_domain_supply_net PD1 -primary_power_net PG1 -primary_ground_net PG0
[271] Command : associate_supply_set
Description: Associate supply sets
Options :
Example :
associate_supply_set {AON_SS PD1.primary PD2.backup PD3.isolation}
associate_supply_set {ISO_SS U1/PD1.my_iso.isolation_supply}
associate_supply_set ISO_SS -handle U1/PD1.my_iso.isolation_supply
[272] Command : create_supply_port
Description: Creates supply port
Options :
Example : create_supply_port VDD
[273] Command : create_logic_port
Description: Creates port
Options :
Example : create_logic_port port1
[274] Command : connect_supply_net
Description: Creates supply port
Options :
Example : connect_supply_net NET -ports VDD
[275] Command : connect_logic_net
Description: Connect a logic net to logic ports.
Options :
connect_logic_net net_name
-ports port_list
[-reconnect]
Example : connect_logic_net ena -ports {a U1/b}
[276] Command : connect_supply_set
Description: Connect a supply set to particular elements
Options :
connect_supply_set supply_set_ref
{-connect {supply_ function pg_type_list}}*
[-elements element_list]
[-exclude_elements exclude_list]
[-transitive [<TRUE | FALSE>]]
Example : connect_supply_set some_supply_set -elements {U1/U_mem} -connect {power {primary_power}} -connect {ground {primary_ground}}
[277] Command : create_power_switch
Description: Creates power switch
Example 1- Simple switch
This switch model has a single supply input and a single control input. The switch is either on or off, based
on the control input value. Since net names are not specified for each port, connect_supply_net (see 6.11)
can be used to connect a net to each port.
create_power_switch simple_switch
-output_supply_port {vout}
-input_supply_port {vin}
-control_port {ss_ctrl}
-on_state {ss_on vin { ss_ctrl }}
-off_state {ss_off { ! ss_ctrl }}
The following is a variant of the simple switch in which the nets associated with the ports are defined as part
of the create_power_switch command (see 6.18).
create_power_switch simple_switch2
-output_supply_port {vout VDD_SW}
-input_supply_port {vin VDD}
-control_port {ss_ctrl sw_ena}
-on_state {ss_on vin { ss_ctrl }}
-off_state {ss_off { ! ss_ctrl }}
Example 2-Two-stage switch
This switch model represents a switch that turns on in two stages. The switch has one supply input and two
control inputs. One control input represents the enable for the first stage; the other represents the control for
the second stage. When only the first control is on, the switch output is in a partial on state; when the second
is on, the switch output is in a fully on state. The switch is off if neither control input is on.
create_power_switch two_stage_switch
-output_supply_port {vout}
-input_supply_port {vin}
-control_port {trickle_ctrl}
-control_port {main_ctrl}
-on_partial_state {ts_ton vin { trickle_ctrl }}
-on _state {ts_mon vin { main_ctrl }}
-off_state {ts_off { ! trickle_ctrl && ! main_ctrl }}
The following is a variant of the two-stage switch model in which an -ack_port signals completion of the
switch turning on. The time required for the switch to turn on is modeled by the -ack_delay. Since an
-ack_port is involved, the command needs to include specification of the supply set that powers the logic
driving the ack signal. The ack signal is defined separately. In this model, as in the preceding simple switch
variant, the supply and control ports are associated with corresponding nets, so they do not need to be
connected in a separate step.
create_power_switch two_stage_switch2
-output_supply_port {vout VDD_SW}
-input_supply_port {vin VDD}
-control_port {trickle_ctrl t_ena}
-control_port {main_ctrl m_ena}
-on_partial_state {ts_ton vin { trickle_ctrl }}
-on _state {ts_mon vin { main_ctrl }}
-off_state {ts_off { ! trickle_ctrl && ! main_ctrl }}
-ack_port {ts_ack 1}
-ack_delay {ts_ack 100ns}
-supply_set ss_aon
Example 3-Muxed switch
This switch model represents a mux that determines which of two different input supplies is connected to the
output supply port at any given time. The two input supplies can be driven by different root supply drivers
and may have different state/voltage values. One control input determines which of the two input supplies is
selected; the other control input gates the selected supply to the output supply.
create_power_switch muxed_switch
-output_supply_port {vout}
-input_supply_port {vin0}
-input_supply_port {vin1}
-control_port {ms_sel}
-control_port {ms_ctrl}
-on_state {ms_on0 vin0 { ms_ctrl && ! ms_sel }}
-on_state {ms_on1 vin1 { ms_ctrl && ms_sel }}
-off_state {ms_off { ! ms_ctrl }}
The following is a variant of the muxed switch in which there are two independent selection control inputs,
and an error state is defined to ensure mutual exclusion.
create_power_switch muxed_switch2
-output_supply_port {vout}
-input_supply_port {vin0}
-input_supply_port {vin1}
-control_port {ms_sel0}
-control_port {ms_sel1}
-control_port {ms_ctrl}
-on_state {ms_on0 vin0 { ms_ctrl && ms_sel0 }}
-on_state {ms_on1 vin1 { ms_ctrl && ms_sel1 }}
-off_state {ms_off { ! ms_ctrl }}
-error_state {conflict { ms_sel0 && ms_sel1 }}
Example 4-Overlapping muxed switch
This switch model represents a supply mixer that allows a smooth transition between two different supplies.
Like the muxed switch, it has two supply inputs and both selecting and gating control inputs, but in this case
it can select both input supplies at the same time. The input supplies may have different states, and may even
be driven by different root supply drivers, provided that their voltages are the same when both inputs are
enabled (in an on state or on_partial state).
create_power_switch overlapping_muxed_switch
-output_supply_port {vout}
-input_supply_port {vin0}
-input_supply_port {vin1}
-control_port {oms_sel0}
-control_port {oms_sel1}
-control_port {oms_ctrl}
-on_state {oms_on0 vin0 { oms_ctrl && oms_sel0 }}
-on_state {oms_on1 vin1 { oms_ctrl && oms_sel1 }}
-off_state {oms_off { !oms_ctrl || { !oms_sel0 && !oms_sel1 } }}
[278] Command : set_isolation
Description: sets isolation cells
Options :
set_isolation parent_strategy
-domain pda
-elements {a b c d}
-isolation_supply {pda_isolation_supply}
-clamp_value {1}
-applies_to outputs -sink pdb
set_isolation parent_strategy -update
-domain pda
-isolation_signal cpu_iso
-isolation_sense low -location parent
[279] Command : set_isolation_control
Description: sets isolation controls
Options :
set_isolation_control crc_iso_out -domain CRC_GEN -isolation_signal power_controller/crc_iso -location parent
[280] Command : set_retention
Description: Defines retention strategies
Options :
set_retention retention_name
-domain domain_name
-elements element_list
-exclude_elements exclude_list
-retention_supply ret_supply_set
-no_retention
-save_signal {logic_net <high | low | posedge | negedge>}
-restore_signal {logic_net <high | low | posedge | negedge>}
-save_condition {boolean_expression}
-restore_condition {boolean_expression}
-retention_condition {boolean_expression}
-use_retention_as_primary
-parameters {<RET_SUP_COR | NO_RET_SUP_COR | SAV_RES_COR | NO_SAV_RES_COR> *}
-instance {{instance_name signal_name}*}
-update
-retention_power_net net_name
-retention_ground_net net_name
[281] Command : set_retention_control
Description: Defines retention controls
Options :
set_retention_control crc_retain -domain CRC_GEN -save_signal {power_controller/crc_save high} -restore_signal {power_controller/crc_restore high}
[282] Command : use_interface_cell
Description: Specify the functional model and a list of implementation targets for isolation and level-shifting
Options :
use_interface_cell interface_implementation_name
-strategy list_of_isolation_level_shifter_strategies
-domain domain_name
-lib_cells lib_cell_list
[-port_map {{port net_ref } *}]
[-elements element_list]
[-exclude_elements exclude_list]
[-applies_to_clamp <0 | 1 | any | Z | latch | value>]
[-update_any <0 | 1 | known | Z | latch | value>]
[-force_function]
[-inverter_supply_set list]
[283] Command : map_retention_cell
Description: Maps reention cells
Options :
map_retention_cell retention_name_list
-domain domain_name
-elements element_list
-exclude_elements exclude_list
-lib_cells lib_cell_list
-lib_cell_type lib_cell_type
-lib_model_name name
-port_map {{port_name net_ref } *}
[284] Command : map_repeater_cell
Description:
Options :
[285] Command : map_power_switch
Description:
Options :
[286] Command : set_retention_elements
Description: Sets the retention elemets
Options :
set_retention_elements retention_list_name
-elements element_list
[-applies_to <required | not_optional | not_required | optional>]
[-exclude_elements exclude_list]
[-retention_purpose <required | optional>]
[-transitive [<TRUE | FALSE>]]
Example :
set_retention_elements ret_chk_list -elements {proc_1 sig_a}
[287] Command : apply_power_model
Description: Associates power mmodels with instance
Options :
apply_power_model power_model_name
[-elements instance_name_list]
[-supply_map {{lower_scope_supply_set upper_scope_supply_set}*}]
[-parameters {{power_model_ parameter design_object}*}]
If -elements is specified, each instance name in the instance name list shall be a simple name or a hierarchical name rooted in the current scope. In this case, for the duration of the apply_power_model command, the current scope and design top instance are both set to the instance specified by the instance name and the design top module is set to the module type of that instance. If -elements is not specified, then the system-level IP power model binding is not supported and the specified supply association is applied to all instantiations of targeted macro cells by the specified power model (see 6.11) under the current scope. The general precedence rules in 5.7 apply here as well. When the apply_power_model command completes, the current scope, design top instance, and design top module all revert to their previous values. Each pair in the -supply_map option implies an associate_supply_set command (see 6.10) of the following general form:
associate_supply_set {lower_scope_supply_set upper_scope_supply_set}
The arguments of the -supply_map option need to be such that the implied associate_supply_set commands are legal.
Example :
apply_power_model upf_model -elements I1 -supply_map {{PD.ssh1 ss1} {PD.ssh2 ss2}}
[288] Command : create_power_state_group
Description: Create a name for a group of related power states.
Options :
create_power_state_group group_name
where group_name is the simple name of the group to be created in the current scope
Example :
create_power_state_group CPU_cluster
add_power_state -group CPU_cluster
-state {RUN1
-logic_expr {CPU0==RUN && CPU1==SHD && CPU2==SHD && CPU3==SHD}}
-state {RUN2
-logic_expr {CPU0==RUN && CPU1==RUN && CPU2==SHD && CPU3==SHD}}
-state {RUN3
-logic_expr {CPU0==RUN && CPU1==RUN && CPU2==RUN && CPU3==SHD}}
-state {RUN4
-logic_expr {CPU0==RUN && CPU1==RUN && CPU2==RUN && CPU3==RUN}}
[289] Command : set_correlated
Description: To declare that supply nets or sets voltage variation ranges are to be treated as correlated when being compared; min to min and max to max.
Options :
set_correlated
[-nets {{supply_net_name_list}*}]
[-sets {{supply_set_name_list}*}]
Example :
set_correlated -nets {{VDD1 VDD2}}
set_correlated -nets {{VDD1 VDD2} {VDD3 VDD4}}
set_correlated -sets {{SS1 SS2}}
[290] Command : set_equivalent
Description: Declare that supply nets or supply sets are electrically or functionally equivalent.
Options :
set_equivalent [-function_only]
[-nets {{supply_net_name_list}*}]
[-sets {{supply_set_name_list}*}]
Example :
set_equivalent -nets { vss1 vss2 ground }
set_equivalent -function_only -nets { vdd_wall vdd_battery }
set_equivalent -function_only -sets { /sys/aon_ss mem/PD1.core_ssh }
[291] Command : set_variation
Description: Specify the variation range for a supply source.
Options :
set_variation
-supply supply_name_list
-range { low_ factor high_ factor }
Example :
set_variation -supply { vss1 vss2 ground } -range { 0.95 1.05 }
[292] Command : set_level_shifter
Description: describes leel shifter
Options :
set_level_shifter strategy_name
-domain domain_name
-elements element_list
-exclude_elements exclude_list
-source <source_domain_name | source_supply_ref>
-sink <sink_domain_name | sink_supply_ref>
-use_equivalence <TRUE | FALSE>
-applies_to <inputs | outputs | both>
-applies_to_boundary <lower | upper | both>
-rule <low_to_high | high_to_low | both>
-threshold <value>
-no_shift
-force_shift
-location <self | other | parent | fanout>
-input_supply supply_set_ref
-output_supply supply_set_ref
-internal_supply supply_set_ref
-name_prefix pattern
-name_suffix pattern
-instance {{instance_name port_name}*}
-update
[293] Command : set_repeater
Description: Specify a repeater (buffer) strategy.
Options :
set_repeater strategy_name
-domain domain_name
[-elements element_list]
[-exclude_elements exclude_list]
[-source <source_domain_name | source_supply_ref > ]
[-sink <sink_domain_name | sink_supply_ref > ]
[-use_equivalence [<TRUE | FALSE>]]
[-applies_to <inputs | outputs | both>]
[-applies_to_boundary <lower | upper | both>]
[-repeater_supply supply_set_ref ]
[-name_prefix string]
[-name_suffix string]
[-instance {{instance_name port_name}*}]
[-update]
[294] Command : set_port_attributes
Description: Sets port attributes
Options :
Example : set_port_attributes
[295] Command : set_design_attributes
Description: Sets design attributes
Options :
Example : set_design_attributes
[296] Command : add_power_state
Description: Adds power state
Options :
Example : add_power_state
[297] Command : add_port_state
Description: Adds port state
Options :
Example :
add_port_state port_name
{-state {name <nom | off>}}*
[298] Command : create_pst
Description: Create power state
Options :
Example :
create_pst table_name -supplies supply_list
create_pst MyPowerStateTable -supplies {PN1 PN2 SOC/OTC/PN3}
[299] Command : add_pst_state
Description: Add power state
Options :
create_pst pt -supplies { PN1 PN2 SOC/OTC/PN3 }
add_pst_state s1 -pst pt -state { s08 s08 s08 }
add_pst_state s2 -pst pt -state { s08 s08 off }
add_pst_state s3 -pst pt -state { s08 s09 off }
Example :
add_pst_state table_name -supplies supply_list
create_pst MyPowerStateTable -supplies {PN1 PN2 SOC/OTC/PN3}
[300] Command : begin_power_model
Description: Defines Power Model
Options :
Example :
begin_power_model upf_model -for cellA
create_power_domain PD1 -elements {.} -supply {ssh1} -supply {ssh2}
set_design_attributes -models MEMSRAM_1024X32 -is_hard_macro TRUE
end_power_model
[301] Command : end_power_model
Description: End power model definition
Options :
Example :
begin_power_model upf_model -for cellA
create_power_domain PD1 -elements {.} -supply {ssh1} -supply {ssh2}
set_design_attributes -models MEMSRAM_1024X32 -is_hard_macro TRUE
end_power_model
[302] Command : find_objects
Description: Find objects of specified type
Options :
Example :
find_objects A/B/D -pattern *BW1* -object_type inst -transitive TRUE
[303] Command : define_always_on_cell
Description: The define_always_on_cell library command identifies the library cells having more than one set of power and ground pins that can remain functional even when the supply to the switchable power or ground pin is switched off.
Options :
Example : define_always_on_cell -cells aon_cell -isolated_pins { {pin1 pin2} {pin3}} -enable {!iso1 ""}
[304] Command : define_isolation_cell
Description: The define_isolation_cell library command identifies the library cells that can be used for isolation in a design with power gating.
By default, the output pin of a multi-rail isolation cell is related to the non-switchable power and ground pins. The non-enable input pin is related to the switchable power and ground pins. A multi-rail isolation cell is a cell with two power or ground pins.
Options :
define_isolation_cell
-cells cell_list
[-power power_ pin]
[-ground ground_ pin]
{-enable pin [-clamp_cell <high | low>]
| -pin_groups {{input_pin output_ pin [enable_ pin]}*}
| -no_enable <high | low | hold>}
[-always_on_pins pin_list]
[-aux_enables ordered_ pin_list]
[-power_switchable power_ pin] [-ground_switchable ground_ pin]
[-valid_location <source | sink | on | off | any>]
[-non_dedicated]
Example : define_isolation_cell -cells iso_cell1 -power VDD -ground GVSS -enable iso_en -valid_location any
[305] Command : define_level_shifter_cell
Description: The define_level_shifter_cell library command identifies the library cells to use as level-shifter cells, as follows:
--If -input_voltage_range is specified, the -output_voltage_range shall also be specified.
--If -ground_input_range is specified, the -ground_output_range shall also be specified.
--It shall be an error if neither -input_voltage_range nor -ground_input_voltage_range is specified.
If a list of voltage ranges is specified for the input supply voltage, a list of voltage ranges for the output supply voltage with the same number of elements shall also be specified., i.e., each member in the list of input voltage ranges needs to have a corresponding member in the list of output voltage ranges.
By default, the enable and output pins of this cell are related to the output power and output ground pins (specified through the -output_power_pin and -output_ground_pin options). And the non-enable input pin is related to the input power and input ground pins (specified through the -input_power_pin and -input_ground_pin options).
Options :
define_level_shifter_cell
-cells cell_list
[-input_voltage_range {{lower_bound upper_bound}*}]
[-output_voltage_range {{lower_bound upper_bound}*}]
[-ground_input_voltage_range {{lower_bound upper_bound}*}]
[-ground_output_voltage_range {{lower_bound upper_bound}*}]
[-direction <low_to_high | high_to_low | both>]
[-input_power_pin power_ pin]
[-output_power_pin power_ pin]
[-input_ground_pin ground_ pin]
[-output_ground_pin ground_ pin]
[-ground ground_pin] [-power power_ pin]
[-enable pin | -pin_groups {{input_pin output_pin [enable_ pin]}*}]
[-valid_location <source | sink | either | any>]
[-bypass_enable expression] [-multi_stage integer]
Example :
define_level_shifter_cell -cells LSHL -input_voltage_range {{1.0 1.0}} -output_voltage_range {{0.8 0.8}} -direction high_to_low -input_power_pin VH -ground G
[306] Command : define_retention_cell
Description: The define_retention_cell library command identifies the library cells to use as retention cells. The following also apply:
--By default, all pins of this cell are related to the switchable power and ground pins, unless otherwise specified.
--It shall be an error if the save and restore functions both identify the same pin, and the polarity or edge sensitivity are the same for that pin. For example, the following two commands are incorrect:
define_retention_cell -cells My_Ret_Cell1 -restore_function {pg high} -save_function {pg high}
define_retention_cell -cells My_Ret_Cell2 -restore_function {pg posedge} -save_function {pg posedge}
--It shall be an error if the conditions specified in -save_check, -restore_check, or -retention_check conflict with -hold_check. For example, the specification:
-hold_check clk -save_check !clk -restore_check clk
shall be an error since the -hold_check requires the clk signal to hold the same value from the time when the save event occurs to the time when the restore event occurs, but the other two options require the signal clk have different values.
Options :
define_retention_cell
-cells cell_list
-power power_ pin
-ground ground_ pin
[-cell_type string]
[-always_on_pins pin_list]
[-restore_function {{pin <high | low | posedge | negedge}}]
[-save_function {{pin <high | low | posedge | negedge}}]
[-restore_check expression]
[-save_check expression]
[-retention_check expression]
[-hold_check pin_list]
[-always_on_components component_list]
[-power_switchable power_pin]
[-ground_switchable ground_pin]
Example :
define_retention_cell -cells My_Ret_Cell -power VDDC -ground VSS -power_switchable VDD -save_check {!clk} -restore_check {!clk} -save_function {save negedge}
[307] Command : define_power_switch_cell
Description: Identify a power switch or ground-switch cell.
Options :
define_power_switch_cell
-cells cell_list
-type <footer | header>
-stage_1_enable expression
[-stage_1_output expression]
{-power_switchable power_ pin
-power power_ pin
| -ground_switchable ground_pin
[-ground ground_ pin]}
[-stage_2_enable expression
[-stage_2_output expression]]
[-always_on_pins ordered_ pin_list]
[-gate_bias_pin power_ pin]
Example :
define_power_switch_cell -cells 2stage_switch -stage_1_enable !I1 -stage_1_output O1 -stage_2_enable I2 -stage_2_output !O2 -type header
[308] Command : define_diode_clamp
Description: Identify diode cells or cells pins with diode protection.
Options : The define_diode_clamp library command identifies a list of library cells that are power cells, ground cells, or power and ground diode clamp cells, or complex cells that have input pins with built-in clamp diodes.
When -type is ground, then -power is optional. When -type is power, then -ground is optional. When -type is both, then both -power and -ground need to be specified as well.
Example :
define_diode_clamp
-cells cell_list
-data_pins pin_list
[-type <power | ground | both>]
[-power pin]
[-ground pin]
[309] Command : add_parameter
Description: Define parameters for use within the system-level IP power model.
The add_parameter command is used to define parameters for use within a system-level IP power model. The parameter scope is within the power model only and power models and power functions cannot access parameters that are defined outside of the power model in which they are used. Three types of parameters can be defined as follows:
- Build time-used to define parameters that remain unchanged during run time
- Run time-used to define parameters that can change during run time
- Rate-used to define parameters that represent rate-based quantities that can change during run time
Both run time and rate-based parameters can form a part of the sensitivity list for a power function. Any change in the value of such a parameter forces an invocation of the power function and a recalculation of power (or current) consumption. The units in which the parameter is defined are included within the parameter definition. Standard SI units shall be used where required, for parameters that are defined within a system-level IP power model. It shall be an error if:
a) parameter_name has already been defined within the power model
b) A default value of the parameter is not provided
c) A parameter defined using -type buildtime changes value during simulation
Options :
add_parameter parameter_name
-type < buildtime | runtime | rate >
-default value
-description string
Example :
add_parameter process -type buildtime -default 1.0 -description "Process Scaling Factor"
[310] Command : add_state_transition
Description: Define named transitions among power states of an object.
Options :
add_state_transition
[-supply | -domain | -group | -model | -instance] object_name
[-update]
[-transition {transition_name
[-from from_list -to to_list]
[-paired {{from_state to_state}*}]
[-legal | -illegal]
}]*
[-complete]
Example : connect_supply_set some_supply_set -elements {U1/U_mem} -connect {power {primary_power}} -connect {ground {primary_ground}}
[311] Command : add_supply_state
Description: Add states to a supply port, a supply net, or a supply set function
Options :
add_supply_state object_name
{-state {name <nom | off>}}*
Example : add_supply_state PD.primary.power -state {active_state 0.90 } -state {off_state off}
[312] Command : set_partial_on_translation
Description: This command causes translation of PARTIAL_ON to FULL_ON or OFF, as specified by the command
argument, for purposes of evaluating the power state of supply sets and power domains. If this command is
executed in a given run, the state of a supply set is evaluated after PARTIAL_ON is translated to
FULL_ON or OFF for each supply net in the set. If this command is not executed in a given run, no
translation of PARTIAL_ON is performed.
Options :
set_partial_on_translation <OFF | FULL_ON>
Example : set_partial_on_translation FULL_ON
[313] Command : bind_checker
Description: Insert checker modules and bind them to instances.
Options :
bind_checker instance_name
-module checker_name
[-elements element_list]
[-bind_to module [-arch name]]
[-ports {{port_name net_name}*}]
[-parameters {{param_name param_value}*}]
Example :
checker_module with following interface:
module checker_module ( save, restore, reset_a, clock_a );
input save, restore, reset_a, clock_a;
... different mutex assertions ...
endmodule
The bind_checker command would look like the following:
bind_checker mutex_checker_inst -module checker_module -ports { {save PDA.test_retention.save_signal } { restore PDA.test_retention.restore_signal } { reset_a reset_a } { clock_a clock_a } }
[314] Command : create_hdl2upf_vct
Description: Define a VCT that can be used in converting HDL logic values into state type values
Options :
create_hdl2upf_vct vct_name
-hdl_type {<vhdl | sv> [typename]}
-table {{from_value to_value}*}
Example :
create_hdl2upf_vct
vlog2upf_vss
-hdl_type {sv reg}
-table {{X OFF} {0 FULL_ON} {1 OFF} {Z PARTIAL_ON}}
create_hdl2upf_vct
stdlogic2upf_vss
-hdl_type {vhdl std_logic}
-table {{'U' OFF}
{'X' OFF}
{'0' OFF}
{'1' FULL_ON}
{'Z' PARTIAL_ON}
{'W' OFF}
{'L' OFF}
{'H' FULL_ON}
{'-' OFF}}
[315] Command : create_upf2hdl_vct
Description: Define VCT that can be used in converting UPF supply_net_type values into HDL logic
values.
Options :
create_upf2hdl_vct vct_name
-hdl_type {<vhdl | sv> [typename]}
-table {{from_value to_value}*}
Example :
create_upf2hdl_vct upf2vlog_vdd
-hdl_type {sv}
-table {{OFF X} {FULL_ON 1} {PARTIAL_ON 0}}
create_upf2hdl_vct upf2vhdl_vss
-hdl_type {vhdl std_logic}
-table {{OFF 'X'} {FULL_ON '1'} {PARTIAL_ON 'H'}}
[316] Command : load_simstate_behavior
Description: Load the simstate behavior defaults for a library.
Options :
load_simstate_behavior lib_name -file file_list
Example :
load_simstate_behavior library1 -file simstate_file.upf
[317] Command : name_format
Description: Define the format for constructing names of implicitly created objects.
Options :
name_format
[-isolation_prefix pattern] [-isolation_suffix pattern]
[-level_shift_prefix pattern] [-level_shift_suffix pattern]
[-implicit_supply_suffix string]
[-implicit_logic_prefix string] [-implicit_logic_suffix string]
Example :
Syntax example
name_format -isolation_prefix "MY_ISO_" -isolation_suffix ""
A signal, MY_ISO_FOO, is created and connected to a new cell's output (to isolate the existing net FOO).
name_format level_shift_prefix "shift_%d_%s_" level_shift_suffix "%i_UPF_LS"
[318] Command : set_simstate_behavior
Description: Specify the simulation simstate behavior for a model or library.
Options :
set_simstate_behavior <ENABLE | DISABLE>
[-lib name]
[-models model_list]
[-elements element_list]
[-exclude_elements exclude_list]
Example : set_simstate_behavior ENABLE -lib library1 -models ANDX7_non_power_aware
[319] Command : save_upf
[320] Command : describe_state_transition
Description:
Options : describe_state_transition transition_name -object object_name
[-from from_list -to to_list]
[-paired {{from_state to_state}*}]
[-legal | -illegal]
Example : describe_state_transition turn_on -object PdA -from {SLEEP_MODE} -to {HIGH_SPEED_MODE} -illegal
[321] Command : upf_query_object_properties
[322] Command : upf_query_object_type
[323] Command : upf_object_in_class
[324] Command : upf_query_object_pathname
[325] Command : query_upf
[326] Command : upf_iter_get_next
[327] Command : upf_get_value_str
[328] Command : upf_get_value_int
[329] Command : upf_get_value_real
[330] Command : upf_get_label_upfSupplyTypeT
[331] Command : get_supply_value
[332] Command : get_supply_voltage
[333] Command : get_supply_on_state
[334] Command : get_supply_state
[335] Command : upf_set_value_int
[336] Command : upf_set_value_upfSupplyTypeT
[337] Command : supply_on
[338] Command : supply_off
[339] Command : supply_partial_on
[340] Command : set_supply_state
[341] Command : set_power_state_by_handle
[342] Command : set_power_state
[343] Command : upf_create_object_mirror
[344] Command : upf_query_object_type
[345] Command : upf_handle_in_class
[346] Command : upf_query_object_pathname
[347] Command : upf_convert_real_volts_to_int_uvolts
[348] Command : upf_convert_int_uvolts_to_real_volts
[349] Command : upf_convert_int_uvolts_to_real_volts
[350] Command : decompile
Description: Decompiles object passed as argument
Options :
Example : decompile $pd
[351] Command : decompile_upf_model
Description: Decompiles entire database into a file
Options :
Example : decompile_upf_model foo.upf
[352] Command : replace_variables
[353] Command : enable_debug
[354] Command : disable_debug
[355] Command : add_to_collection
Description:
Options :
Example : add_to_collection
[356] Command : all_clocks
Description:
Options :
Example : all_clocks
[357] Command : all_inputs
Description:
Options :
Example : all_inputs
[358] Command : all_outputs
Description:
Options :
Example : all_outputs
[359] Command : all_registers
Description:
Options :
Example : all_registers
[360] Command : check_timing
Description:
Options :
Example : check_timing
[361] Command : create_clock
Description:
Options :
Example : create_clock
[362] Command : create_generated_clock
Description:
Options :
Example : create_generated_clock
[363] Command : create_report_histogram
Description:
Options :
Example : create_report_histogram
[364] Command : create_slack_histogram
Description:
Options :
Example : create_slack_histogram
[365] Command : create_timing_netlist
Description:
Options :
Example : create_timing_netlist
[366] Command : create_timing_summary
Description:
Options :
Example : create_timing_summary
[367] Command : create_voltage_area
Description:
Options :
Example : create_voltage_area
[368] Command : current_design
Description:
Options :
Example : current_design
[369] Command : current_instance
Description:
Options :
Example : current_instance
[370] Command : delete_timing_netlist
Description:
Options :
Example : delete_timing_netlist
[371] Command : derive_clocks
Description:
Options :
Example : derive_clocks
[372] Command : enable_ccpp_removal
Description:
Options :
Example : enable_ccpp_removal
[373] Command : enable_sdc_extension_collections
Description:
Options :
Example : enable_sdc_extension_collections
[374] Command : get_available_operating_conditions
Description:
Options :
Example : get_available_operating_conditions
[375] Command : get_cell_info
Description:
Options :
Example : get_cell_info
[376] Command : get_cells
Description:
Options :
Example : get_cells
[377] Command : get_clock_domain_info
Description:
Options :
Example : get_clock_domain_info
[378] Command : get_clock_fmax_info
Description:
Options :
Example : get_clock_fmax_info
[379] Command : get_clock_info
Description:
Options :
Example : get_clock_info
[380] Command : get_clocks
Description:
Options :
Example : get_clocks
[381] Command : get_datasheet
Description:
Options :
Example : get_datasheet
[382] Command : get_default_sdc_file_names
Description:
Options :
Example : get_default_sdc_file_names
[383] Command : get_edge_info
Description:
Options :
Example : get_edge_info
[384] Command : get_edge_slacks
Description:
Options :
Example : get_edge_slacks
[385] Command : get_fanouts
Description:
Options :
Example : get_fanouts
[386] Command : get_keepers
Description:
Options :
Example : get_keepers
[387] Command : get_lib_cells
Description:
Options :
Example : get_lib_cells
[388] Command : get_lib_pins
Description:
Options :
Example : get_lib_pins
[389] Command : get_libs
Description:
Options :
Example : get_libs
[390] Command : get_min_pulse_width
Description:
Options :
Example : get_min_pulse_width
[391] Command : get_net_info
Description:
Options :
Example : get_net_info
[392] Command : get_nets
Description:
Options :
Example : get_nets
[393] Command : get_node_info
Description:
Options :
Example : get_node_info
[394] Command : get_nodes
Description:
Options :
Example : get_nodes
[395] Command : get_object_info
Description:
Options :
Example : get_object_info
[396] Command : get_operating_conditions
Description:
Options :
Example : get_operating_conditions
[397] Command : get_operating_conditions_info
Description:
Options :
Example : get_operating_conditions_info
[398] Command : get_partition_info
Description:
Options :
Example : get_partition_info
[399] Command : get_partitions
Description:
Options :
Example : get_partitions
[400] Command : get_path
Description:
Options :
Example : get_path
[401] Command : get_path_info
Description:
Options :
Example : get_path_info
[402] Command : get_pin_info
Description:
Options :
Example : get_pin_info
[403] Command : get_pins
Description:
Options :
Example : get_pins
[404] Command : get_point_info
Description:
Options :
Example : get_point_info
[405] Command : get_port_info
Description:
Options :
Example : get_port_info
[406] Command : get_ports
Description:
Options :
Example : get_ports
[407] Command : get_register_info
Description:
Options :
Example : get_register_info
[408] Command : get_registers
Description:
Options :
Example : get_registers
[409] Command : get_timing_paths
Description:
Options :
Example : get_timing_paths
[410] Command : locate
Description:
Options :
Example : locate
[411] Command : query_collection
Description:
Options :
Example : query_collection
[412] Command : read_sdc
Description:
Options :
Example : read_sdc
[413] Command : remove_annotated_delay
Description:
Options :
Example : remove_annotated_delay
[414] Command : remove_clock
Description:
Options :
Example : remove_clock
[415] Command : remove_clock_groups
Description:
Options :
Example : remove_clock_groups
[416] Command : remove_clock_latency
Description:
Options :
Example : remove_clock_latency
[417] Command : remove_clock_uncertainty
Description:
Options :
Example : remove_clock_uncertainty
[418] Command : remove_disable_timing
Description:
Options :
Example : remove_disable_timing
[419] Command : remove_from_collection
Description:
Options :
Example : remove_from_collection
[420] Command : remove_input_delay
Description:
Options :
Example : remove_input_delay
[421] Command : remove_output_delay
Description:
Options :
Example : remove_output_delay
[422] Command : report_advanced_io_timing
Description:
Options :
Example : report_advanced_io_timing
[423] Command : report_bottleneck
Description:
Options :
Example : report_bottleneck
[424] Command : report_clock_fmax_summary
Description:
Options :
Example : report_clock_fmax_summary
[425] Command : report_clocks
Description:
Options :
Example : report_clocks
[426] Command : report_clock_transfers
Description:
Options :
Example : report_clock_transfers
[427] Command : report_datasheet
Description:
Options :
Example : report_datasheet
[428] Command : report_ddr
Description:
Options :
Example : report_ddr
[429] Command : report_exceptions
Description:
Options :
Example : report_exceptions
[430] Command : report_max_skew
Description:
Options :
Example : report_max_skew
[431] Command : report_metastability
Description:
Options :
Example : report_metastability
[432] Command : report_min_pulse_width
Description:
Options :
Example : report_min_pulse_width
[433] Command : report_net_delay
Description:
Options :
Example : report_net_delay
[434] Command : report_net_timing
Description:
Options :
Example : report_net_timing
[435] Command : report_partitions
Description:
Options :
Example : report_partitions
[436] Command : report_path
Description:
Options :
Example : report_path
[437] Command : report_rskm
Description:
Options :
Example : report_rskm
[438] Command : report_sdc
Description:
Options :
Example : report_sdc
[439] Command : report_skew
Description:
Options :
Example : report_skew
[440] Command : report_tccs
Description:
Options :
Example : report_tccs
[441] Command : report_timing
Description:
Options :
Example : report_timing
[442] Command : report_ucp
Description:
Options :
Example : report_ucp
[443] Command : reset_design
Description:
Options :
Example : reset_design
[444] Command : reset_timing_derate
Description:
Options :
Example : reset_timing_derate
[445] Command : set_active_clocks
Description:
Options :
Example : set_active_clocks
[446] Command : set_annotated_delay
Description:
Options :
Example : set_annotated_delay
[447] Command : set_case_analysis
Description:
Options :
Example : set_case_analysis
[448] Command : set_clock_gating_check
Description:
Options :
Example : set_clock_gating_check
[449] Command : set_clock_groups
Description:
Options :
Example : set_clock_groups
[450] Command : set_clock_latency
Description:
Options :
Example : set_clock_latency
[451] Command : set_clock_sense
Description:
Options :
Example : set_clock_sense
[452] Command : set_clock_transition
Description:
Options :
Example : set_clock_transition
[453] Command : set_clock_uncertainty
Description:
Options :
Example : set_clock_uncertainty
[454] Command : set_data_check
Description:
Options :
Example : set_data_check
[455] Command : set_disable_timing
Description:
Options :
Example : set_disable_timing
[456] Command : set_drive
Description:
Options :
Example : set_drive
[457] Command : set_driving_cell
Description:
Options :
Example : set_driving_cell
[458] Command : set_false_path
Description:
Options :
Example : set_false_path
[459] Command : set_fanout_load
Description:
Options :
Example : set_fanout_load
[460] Command : set_hierarchy_separator
Description:
Options :
Example : set_hierarchy_separator
[461] Command : set_ideal_latency
Description:
Options :
Example : set_ideal_latency
[462] Command : set_ideal_network
Description:
Options :
Example : set_ideal_network
[463] Command : set_ideal_transition
Description:
Options :
Example : set_ideal_transition
[464] Command : set_input_delay
Description:
Options :
Example : set_input_delay
[465] Command : set_input_transition
Description:
Options :
Example : set_input_transition
[466] Command : set_level_shifter_strategy
Description:
Options :
Example : set_level_shifter_strategy
[467] Command : set_level_shifter_threshold
Description:
Options :
Example : set_level_shifter_threshold
[468] Command : set_load
Description:
Options :
Example : set_load
[469] Command : set_logic_one
Description:
Options :
Example : set_logic_one
[470] Command : set_logic_zero
Description:
Options :
Example : set_logic_zero
[471] Command : set_max_area
Description:
Options :
Example : set_max_area
[472] Command : set_max_capacitance
Description:
Options :
Example : set_max_capacitance
[473] Command : set_max_delay
Description:
Options :
Example : set_max_delay
[474] Command : set_max_fanout
Description:
Options :
Example : set_max_fanout
[475] Command : set_max_skew
Description:
Options :
Example : set_max_skew
[476] Command : set_max_time_borrow
Description:
Options :
Example : set_max_time_borrow
[477] Command : set_max_transition
Description:
Options :
Example : set_max_transition
[478] Command : set_min_capacitance
Description:
Options :
Example : set_min_capacitance
[479] Command : set_min_delay
Description:
Options :
Example : set_min_delay
[480] Command : set_min_pulse_width
Description:
Options :
Example : set_min_pulse_width
[481] Command : set_multicycle_path
Description:
Options :
Example : set_multicycle_path
[482] Command : set_net_delay
Description:
Options :
Example : set_net_delay
[483] Command : set_operating_conditions
Description:
Options :
Example : set_operating_conditions
[484] Command : set_output_delay
Description:
Options :
Example : set_output_delay
[485] Command : set_port_fanout_number
Description:
Options :
Example : set_port_fanout_number
[486] Command : set_propagated_clock
Description:
Options :
Example : set_propagated_clock
[487] Command : set_resistance
Description:
Options :
Example : set_resistance
[488] Command : set_scc_mode
Description:
Options :
Example : set_scc_mode
[489] Command : set_sense
Description:
Options :
Example : set_sense
[490] Command : set_time_format
Description:
Options :
Example : set_time_format
[491] Command : set_timing_derate
Description:
Options :
Example : set_timing_derate
[492] Command : set_units
Description:
Options :
Example : set_units
[493] Command : set_voltage
Description:
Options :
Example : set_voltage
[494] Command : set_wire_load_min_block_size
Description:
Options :
Example : set_wire_load_min_block_size
[495] Command : set_wire_load_mode
Description:
Options :
Example : set_wire_load_mode
[496] Command : set_wire_load_model
Description:
Options :
Example : set_wire_load_model
[497] Command : set_wire_load_selection_group
Description:
Options :
Example : set_wire_load_selection_group
[498] Command : timing_netlist_exist
Description:
Options :
Example : timing_netlist_exist
[499] Command : update_timing_netlist
Description:
Options :
Example : update_timing_netlist
[500] Command : use_timequest_style_escaping
Description:
Options :
Example : use_timequest_style_escaping
[501] Command : write_sdc
Description:
Options :
Example : write_sdc
Download Latest Version
DesignPlayer-linux.x86_64.tar.gz (592.7 MB)
