| Name | Modified | Size | Downloads / Week |
|---|---|---|---|
| Parent folder | |||
| README.md | 2026-06-05 | 5.5 kB | |
| v0.2.0 - first community release source code.tar.gz | 2026-06-05 | 3.9 MB | |
| v0.2.0 - first community release source code.zip | 2026-06-05 | 4.4 MB | |
| Totals: 3 Items | 8.3 MB | 0 | |
cuda-oxide v0.2.0 — first community release
cuda-oxide is an experimental rustc backend that compiles CUDA GPU kernels written in pure Rust to PTX, with host and device code in a single source tree built through cargo oxide. It owns the SIMT side of the Rust GPU story (complementary to the Tile DSL work).
The headline is momentum. We open-sourced v0.1.0 on May 7 as a solo alpha. In the four weeks since, the project has taken 37 pull requests from 23 contributors, spanning compiler correctness, new device capabilities, host-runtime safety, packaging, and documentation. v0.2.0 is assembled almost entirely from that contributed work.
What landed, at a high level
- Reach. Kernels now embed directly in the host binary with a typed launch API, so a Rust GPU program is a single self-contained executable.
- New capability. CUDA constant memory and additional device math (
max/min,atan) landed through community PRs, widening what real kernels can express. - Trust. A class of silent miscompiles now fails loudly at build time rather than producing wrong results, and the host runtime gained explicit memory-safety contracts.
- Onboarding. A dev container and a Nix flake make first-build friction near zero, which is what is converting drive-by interest into PRs.
- Interop. A working cuTile ↔ SIMT inter-kernel example demonstrates the Tile-to-SIMT handoff on a shared stream, the integration point we own in the broader CUDA-Rust strategy.
- Upstream alignment. Migrated the LLVM dialect onto upstream
pliron-llvm, retiring our in-tree fork in favour of tracking the community project.
Highlights
New device & compiler features
- CUDA constant memory via
#[constant]/Constant<T>(PTX.const, addrspace 4) with generated host setters. - New device math via libdevice:
f32::max/f32::min, andatan/atan2forf32andf64. - A
globaltimer()device intrinsic for cross-SM timing. - TypeId-based kernel PTX naming and a single-byval kernel-entry ABI, fixing generic-closure and aggregate-parameter launches.
Embedded kernels & a typed launch API
- A new
oxide-artifactsbundle format embeds generated PTX / NVVM-IR / LTOIR / cubin directly into the host binary, so kernels load straight from the running executable with no separate.ptxfile. - A
#[cuda_module]proc-macro generates a typed, per-kernel launch surface (&[T]maps to&DeviceBuffer<T>), and by-value closure launches now marshal correctly acrossFn/FnMut/FnOnce.
Correctness & soundness
- Several silent miscompiles now fail loudly at build time instead of producing wrong PTX (dropped
wgmmaaccumulate, elided destructors, swallowed statements). - Fixed niched
Option<NonZero<T>>/Option<&T>Transmutes (thestep_bymiscompile), tuple-returning device functions, and arithmetic-traitOutputresolution on aggregate operands. - Device-codegen panics now print a clean cuda-oxide diagnostic instead of a rustc ICE banner.
Host runtime
- A
DeviceCopysafety contract on all device transfers, pinned (page-locked) host buffers with stream-ordered transfers, propagated async errors, and a rawCUmoduleescape hatch for driver interop. - Fixed a
DeviceBufferallocator mismatch and added CUDA 12.8 / 13 and aarch64 compatibility.
Compiler internals
- Migrated onto upstream
pliron-llvm. The in-treedialect-llvmcrate has been retired and replaced with the communitypliron-llvmdialect frompliron-org/pliron; the local crate is renameddialect-llvm→llvm-exportto reflect its narrower remaining role (textual LLVM-IR / bitcode emission forlibnvvmandllc). pliron is pinned to acuda-oxide-llvm-additionsbranch so we can land additions upstream incrementally while keeping the trunk aligned. - The textual LLVM-IR exporter was refactored into a module (byte-identical output), with correctness fixes for global-symbol (addressof) export and new
selectemission, plus expandedmir-lowertest coverage.
Build, CLI, and developer experience
cargo oxidenow respects yourRUSTFLAGS, nvcc host compiler, andCUDA_HOME; resolvesllcfrom the Rust toolchain; auto-detects the run target GPU; and invalidates a stale backend cache on upgrade.- A reproducible dev container and a Nix flake (
nix run .#new) for one-command onboarding. - A cuTile ↔ SIMT inter-kernel interop example.
Documentation
- A complete LLVM 21 / clang install path for Ubuntu 24.04 and DGX-OS / DGX Spark, plus book and troubleshooting refreshes.
- Doctest failures and rustdoc warnings fixed and gated in CI.
Contributors
Thanks to everyone who shipped code or docs into v0.2.0:
- Alejandro Soto Franco (@alejandro-soto-franco)
- Alex Afshar (@afsharalex)
- Chronara Group (@CG-8663)
- Daniel Lindestad (@lindestad)
- Eden Gilbert Kiseka (@edengilbertus)
- Fabio Baravalle (@fbrv)
- George Amponis (@g-ampo)
- Hiroki Taniai (@nyoki-mtl)
- Ibrahim Rayamah (@iBz-04)
- Jonatan Lindh (@JonatanLindh)
- Joseph Glanville (@josephglanville)
- Magyar Máté András (@Barrow099)
- Mohamed Samir (@mohamedsamirx)
- Onyeka Obi (@MavenRain)
- Paul Zhang (@paulzhng)
- Rob Parolin (@rparolin)
- Robert Forsman (@mutantbob)
- Shaurya Mishra (@winshaurya)
- Stephen Zhang (@hsqStephenZhang)
- sunteng (@goog00)
- Tim Dortmann (@tdortman)
- ur4t (@ur4t)
- Vito Lin (@9-8-7-6)
Status
Early alpha, git-installed (not yet on crates.io), Linux only.