Clash Files

Added:

• Clash.Annotation.SynthesisAtrributes.annotateReg, a function to add synthesis attributes (e.g. ASYNC_REG) to register declarations in the HDL generated by the Clash compiler. #3093
• registerSyncReset #3115

Fixed:

• The Clash.Explicit.Verification.check blackbox now correctly uses the given clock line, not assuming any longer that it is already bound to an identifier in the first place. #2907
• The type of string literals passed to the Clash.Explicit.Verification.check blackbox now matches with the input provided via Clash.Explicit.Verification.name. #2908
• toInteger, toEnum, and fromEnum now correctly sign extend when using Verilog backend. #2729
• dumpVCD now properly aligns the first clock edges in multi-domain designs. #3075
• Removed the limit on the number of traces in dumpVCD. Also removed unnecessary double newlines after 1-bit signals. #3082
• In Clash simulation, pack for Vec and RTree had all bits undefined when the spine of the value had an XException. Now, those elements with defined bits will output those defined bits. In HDL, this was already the case. Example: consider xs = 1 :> undefined :> Nil :: Vec 2 (Unsigned 4) and ys = 1 :> undefined :: Vec 2 (Unsigned 4). xs merely has an undefined element, but ys has an undefined spine: it is a :> constructor that is undefined. pack ys used to be 0b...._.... but is now 0b0001_...., just as pack xs already was. #3114
• Clash drops cached normalization result. #3109
• Fix holdReset glitch behavior for asynchronous resets and wrong hold cycles for sync resets. #3115
• Do not emit source locations if -g is not passed to clash. #3132
• clash-ghc: Remove Opt_LlvmTBAA from unwanted flags. #2508