bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs).
Integration into QSYS from Altera, XIlinx EDK and Vivado IP-Integrator is supported as well.
bel_fft is distributed under the GNU Lesser Public License 2.1.
- Mixed-radix FFT co-processor for (so far radix 4 and radix 2 are supported)
- Master bus interface for memory access
- Slave interface for configuration and control
- Modular architecture
- 32 bit AXI, Avalon and Wishbone interfaces, 64 bit AXI interface
- 32 bit and 16 bit data types
- Can be configured to support four different configurations
- Configuration is done via a GUI
- Twiddle factors as ROM(s)
- Interrupt generation
- Software compatible to Kiss FFT
- Seamless integration into Altera's QSYS and Xilinx Platform Studio
- Written in Verilog
Hi I wanted Exactly same thing Just written in VHDL. So, does anybody know Mixed radix (radix 2 and radix 4) core written in VHDL . Is this kind of core available??
I Use This FFT in my project, and I find a bug. When FFT size is bigger than 1000(for example), the number set to xilinx core generator has the format like 1,000 , and this can not be recognized by core generator and report error(actually should be 1000). So I have to manually generate the myfft_twiddle_rom0.ngc file. Hope to solve this,Thanks!