A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system.

Supports:
UART, SysTick Timer, ADC, SPI, EEPROM, PWM.
Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc.

Tested partially (different modules in each case) on ATMega163/16/32/323/8.

Awards
CodeProject 2010, Third Prize, Hardware and Device Programming

Check the Wiki Page for more details.

Features

  • 8-channel AVR controlled R/C Servo Control
  • Smart Card Reader

Project Samples

Play Video FPGA Flow with AVRILOS AVRILOS Structure Block Diagram CPLD Flow with AVRILOS Hg Branches

Project Activity

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Categories

Frameworks, Operating System Kernels, Embedded Systems

License

Common Development and Distribution License

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Additional Project Details

Intended Audience

Science/Research, Education, Developers, Engineering

Programming Language

C, VHDL/Verilog

Related Categories

C Frameworks, C Operating System Kernels, C Embedded Systems Software, VHDL/Verilog Frameworks, VHDL/Verilog Operating System Kernels, VHDL/Verilog Embedded Systems Software

Registered

2011-05-28
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