A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system.
Supports:
UART, SysTick Timer, ADC, SPI, EEPROM, PWM.
Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc.
Tested partially (different modules in each case) on ATMega163/16/32/323/8.
Awards
CodeProject 2010, Third Prize, Hardware and Device Programming
Check the Wiki Page for more details.
Features
- 8-channel AVR controlled R/C Servo Control
- Smart Card Reader
License
Common Development and Distribution LicenseFollow AVRILOS
You Might Also Like
Our Free Plans just got better! | Auth0 by Okta
You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your secuirty. Auth0 now, thank yourself later.
Rate This Project
Login To Rate This Project
User Reviews
-
Thank you
-
Nice, thank you