This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.

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Additional Project Details

Intended Audience

Information Technology, Science/Research, Telecommunications Industry, Advanced End Users, Developers, Engineering

User Interface

Other toolkit

Programming Language

VHDL/Verilog

Registered

2009-04-17