Python Examples modified by valentin tihhomirov

valentin tihhomirov — Mon, 10 Apr 2017 11:54:19 -0000

This page expands the Scripting section of the documentation.
[TOC]

Accessing modules and selecting their children

Assuming that there is PROC1 in toplevel PARENT, the following code

tl = Toplevel(DMUID.parse("WORK.PARENT"), None)
module = project.getIGM().findModule(tl)

proc1 = module.findChild("PROC1")
printf("%s : %s", module, proc1)

prints

IGModule(duuid=WORK.PARENT(ARCH)) : process (id=PROC1)

To address instantiation which looks like DUT: entity WORK.child; use getSignature:

dut = project.getIGM().findModule(module.findChild("DUT").getSignature());
printf("%s", dut)

Further, we can list the items, declared by the modules and processes

procItems = proc1.getContainer().localItems()
p1Names = [str(l.getId()) for l in procItems]
printf("P1 objects are: %s", ','.join(p1Names))

and filter for variables only

from org.zamia.instgraph import IGObject
import org.zamia.instgraph.IGObject.IGObjectCat
import org.zamia.instgraph.IGObject.OIDir

p1Vars = [str(l.getId()) for l in proc1.getContainer().localItems() 
    if isinstance(l, org.zamia.instgraph.IGObject) and l.getCat() == IGObject.IGObjectCat.VARIABLE]
printf("P1 variables are: %s", ','.join(p1Vars))

To list module ports, use getInterfaceList()

dutPorts = [str(l.getId()) for l in dut.getContainer().getInterfaceList() 
    if isinstance(l, org.zamia.instgraph.IGObject) and l.getCat() == IGObject.IGObjectCat.SIGNAL]
printf("DUT ports are: %s", ','.join(dutPorts))

To obtain the type of container (declared) item, assuming that toplevel declares a RAM signal

for i in module.getContainer().findLocalItems("RAM"):
    printf ("%s has type %s:%s", i, i.getType(), i.getType().getClass())

where getClass prints signal's type = IGTypeStatic, which is used to represent types in IG.

Determining variable range

Given

entity RANGE_TEST is end entity;

architecture RTL of RANGE_TEST is 
  constant c1 : bit_vector(3 to 5) := "011";
  signal s1 : bit_vector(4 to 6) := c1 and "111";
  constant i: Integer := 1;
begin
end architecture;

tl = Toplevel(DMUID.parse("WORK.RANGE_TEST"), None)
module = project.getIGM().findModule(tl)

from org.zamia.instgraph.interpreter import IGInterpreterRuntimeEnv, IGInterpreterCode

for ci in module.getContainer().localItems():
    loc = ci.computeSourceLocation(); 
    t = ci.getType();
    staticType = t.getIndexType() if t.isArray() else t.computeStaticType(IGInterpreterRuntimeEnv(None, project), None, None);
    high = staticType.getStaticHigh(loc);
    low = staticType.getStaticLow(loc);
    ascending = staticType.getStaticAscending(loc);
    printf("%s static type is %s(%s), %s %s %s", ci, staticType, staticType.getClass().getSimpleName(), low, ascending, high);

prints

CONSTANT C1 : ARRAY  3 to 5 OF BIT static type is  3 to 5(IGTypeStatic), 3 TRUE 5
SIGNAL S1 : ARRAY  4 to 6 OF BIT static type is  4 to 6(IGTypeStatic), 4 TRUE 6
CONSTANT I : INTEGER static type is INTEGER(IGTypeStatic), -2147483648 TRUE 2147483647

Evaluation of (rhs) expression

For expression evaluation computeStaticValue can be used. For instance, to obtain initial values of

entity LEFT is end entity;

architecture Arch of LEFT is
    signal b1: boolean;
    constant b2: bit := bit'left;
    constant i1: integer := 1 + 1;
begin
end architecture;

initial values can be obtained with script

from org.zamia.instgraph.interpreter import IGInterpreterRuntimeEnv, IGInterpreterCode
from org.zamia.vhdl.ast.VHDLNode.ASTErrorMode import EXCEPTION

tl = Toplevel(DMUID.parse("WORK.LEFT"), None)
module = project.getIGM().findModule(tl)

#signal = module.getContainer().getInterfaceList()
b1 = module.getContainer().resolveObject("B1")
iv = b1.getInitialValue()
printf("%s: %s := %s ", b1.getId(), b1.getType(), iv)

location = b1.computeSourceLocation()

ic = IGInterpreterCode("Getting initial value", location)
printf("ic = %s", ic)
env = IGInterpreterRuntimeEnv(ic, project)
printf("env = %s", env)

for obj in module.getContainer().localItems():
    iv = obj.getInitialValue() # value is expression actually to be evaluated
    if iv != None: # initial value is defined

        #1: evaluating the iv expression
        iv = " expression %s\n evaluated to %s" % (iv, iv.computeStaticValue(env, EXCEPTION, None))

    else: # init value is undefined -- getting default (left) value

        t = obj.getType().computeStaticType(env, EXCEPTION, None )

        #The core of getting left value. It was misnomered 'generateZ'
        left = org.zamia.instgraph.IGStaticValue.generateZ(t.computeStaticType(env, EXCEPTION, None), location);
        iv = "unspecified, taking %s'left = %s" % (t, left) # must be false

    printf("%s: %s := %s ", obj.getId(), obj.getType(), iv)

which prints

B1: BOOLEAN := unspecified, taking BOOLEAN'left = FALSE 
B2: BIT :=  expression BIT'LEFT evaluated to 0 
I1: INTEGER :=  expression "+"(IGMapping(formal=IGOperationObject(a), actual=1),   IGMapping(formal=IGOperationObject(b), actual=1)) evaluated to 2

Obtaining port mappings

Assuming you have VHDL instantiation

   U8 : entity CLASS.NR2 port map( A => n6, B => n7, Z => y(9));

in C17_VEC toplevel, the following

import org.zamia.instgraph.IGOperationIndex

tl = Toplevel(DMUID.parse("WORK." + "C17_VEC"), None)           
module = project.getIGM().findModule(tl)
u8smt = module.findChild("U8")
printf("top=%s, DUT_GATES = %s", module, u8smt)
u8module = project.getIGM().findModule(u8smt.getSignature())

for i in range(0, u8smt.getNumMappings()):
    def id(igOpObject):
        if isinstance(igOpObject, org.zamia.instgraph.IGOperationIndex):
            #printf("igobject " + igOpObject.getOperand().getObject().getId() + "(" + str(igOpObject.getIndex()) + ")")
            return igOpObject.getOperand().getObject().getId() + "(" + str(igOpObject.getIndex()) + ")"
        return igOpObject.getObject().getId()
    m = u8smt.getMapping(i) ; 
    formal = id(m.getFormal()) ; actual = id(m.getActual()); 
    printf ("formal %s => actual %s", formal, actual)

prints U8 port mapping

formal A => actual N6
formal B => actual N7
formal Z => actual Y(9)

Recent changes to Python Examples

Python Examples modified by valentin tihhomirov

Accessing modules and selecting their children

Determining variable range

Evaluation of (rhs) expression

Obtaining port mappings