From: Guenter B. <gue...@go...> - 2012-01-17 11:56:17
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Saif, On Mon, Jan 16, 2012 at 7:24 PM, Saif Abrar <sye...@gm...> wrote: > hello Guenter, > as part of the VHDL-to-SC conversion, I was looking at the GCD-2 code. > there is a description of a mux as follows: > > entity mux is > port( rst, sLine: in std_logic; > load, result: in std_logic_vector( 3 downto 0 ); > output: out std_logic_vector( 3 downto 0 ) > ); > end mux; > architecture mux_arc of mux is > begin > process( rst, sLine, load, result ) > begin > if( rst = '1' ) then > output <= "0000"; -- do nothing > elsif sLine = '0' then > output <= load; -- load inputs > else > output <= result; -- load results > end if; > end process; > end mux_arc; > > there are few doubts that need clarifications: > 1. in this mux description, the last assignment operation (output <= > result;) is > the 'else' clause of the second if-statement (if sLine = '0'). > Correct? yes > 2. in the IG graph, the second if-statement (if sLine = '0') and the > last assignment operation (output <= result;) > both are coming within the first 'else' statement. > logically, this renders the code as: > IF ( rst = '1' ) then > output <= "0000"; > ELSE > IF sLine = '0' then output <= load; > ELSE nothing; > END-IF > output <= result; //this line will always be executed within this 'else' > END-IF > > I am copying below the DOT code starting from the first if-statement > (rst = '1'). > Please clarify if I am mis-interpreting something in this context. if this is really the IG that is being generated we definitely have a bug here. i dimly remember we had once fixed a bug in the elsif-conversion algorithm, i wonder whether that bugfix was lost or if this is a separate issue. saif, can you (or anyone else) confirm the IG is broken in this case e.g. by running the test case in zamia's simulator? (sorry, don't have time to do that myself right now) best, guenter |