[xtensa-cvscommit] linux/include/asm-xtensa assume.h,1.4,1.5 mmu_context.h,1.4,1.5 pgtable.h,1.9,1.10

[<joe...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv18775/include/asm-xtensa

Modified Files:
	assume.h mmu_context.h pgtable.h 
Log Message:

Replace the 'iitlba' and 'idtlba' instructions (though disable the replacement for now).  Various code improvements based on recent core.h additions.  Answer and remove several XTFIXME comments.

Index: assume.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/assume.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** assume.h	28 Feb 2003 01:53:10 -0000	1.4
--- assume.h	11 Mar 2003 19:16:58 -0000	1.5
***************
*** 21,26 ****
  
  
! #if (XCHAL_HAVE_MMU != 1)
  #error Linux must have an MMU!
  #endif
  
--- 21,45 ----
  
  
! #if (XCHAL_HAVE_TLBS != 1)
  #error Linux must have an MMU!
+ #endif
+ 
+ #if ((XCHAL_ITLB_ARF_WAYS == 0) || (XCHAL_DTLB_ARF_WAYS == 0))
+ #error MMU must have auto-refill ways
+ #endif
+ 
+ /* Linux was ported to Xtensa assuming all auto-refill ways in set 0
+    had the same properties (a very likely assumption).  Multiple sets
+    of auto-refill ways will still work properly, but not as optimally
+    as the Xtensa designer may have assumed.
+ 
+    We make this case a hard #error, killing the kernel build, to alert
+    the developer to this condition (which is more likely an error).
+    You super-duper clever developers can change it to a warning or
+    remove it altogether if you think you know what you're doing.  :)
+ */
+ 
+ #if ((XCHAL_ITLB_ARF_SETS != 1) || (XCHAL_DTLB_ARF_SETS != 1))
+ #error Linux may not use all auto-refill ways as efficiently as you think
  #endif
  

Index: mmu_context.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/mmu_context.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** mmu_context.h	15 Feb 2003 02:02:40 -0000	1.4
--- mmu_context.h	11 Mar 2003 19:17:00 -0000	1.5
***************
*** 25,43 ****
  
  
! /* NTLB_ENTRIES defines the number of auto-refill tlb entries in the
!    itlb.  Function flush_tlb_range() assumes that the dtlb has the
!    same number and just uses NTLB_ENTRIES for both tlbs. */
  
! /* XTFIXME: INDICES_PER_ARG_WAY is a parameter exposed on the GUI.
!    This information really should be available from the CHAL.  Current
!    values are either 4 or 8.  An incorrect setting results is simply
!    suboptimal, not incorrect. */
  
! #define INDICIES_PER_ARF_WAY    4
! #define NTLB_ENTRIES           (XCHAL_ITLB_ARF_WAYS * INDICIES_PER_ARF_WAY)
  
! #if (XCHAL_ITLB_ARF_WAYS != XCHAL_DTLB_ARF_WAYS)
! #error flush_tlb_range() assumes an equal number of ways in itlb and dtlb.
  #endif
  
  /* asid_cache tracks only the ASID[USER_RING] field of the RASID
--- 25,50 ----
  
  
! /* Define the number of entries per auto-refill way in set 0 of both I
!    and D TLBs.  We deal only with set 0 here (an assumption further
!    explained in assume.h).  Also, define the total number of ARF
!    entries in both TLBs. */
  
! #define ITLB_ENTRIES_PER_ARF_WAY  (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES))
! #define DTLB_ENTRIES_PER_ARF_WAY  (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES))
  
! #define ITLB_ENTRIES (ITLB_ENTRIES_PER_ARF_WAY * (XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,WAYS)))
! #define DTLB_ENTRIES (DTLB_ENTRIES_PER_ARF_WAY * (XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,WAYS)))
  
! 
! /* SMALLEST_NTLB_ENTRIES is the smaller of ITLB_ENTRIES and
!    DTLB_ENTRIES.  In practice, they are probably equal.  This macro
!    simplifies function flush_tlb_range(). */
! 
! #if (DTLB_ENTRIES < ITLB_ENTRIES)
! #define SMALLEST_NTLB_ENTRIES  DTLB_ENTRIES
! #else
! #define SMALLEST_NTLB_ENTRIES  ITLB_ENTRIES
  #endif
+ 
  
  /* asid_cache tracks only the ASID[USER_RING] field of the RASID

Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** pgtable.h	5 Mar 2003 17:57:46 -0000	1.9
--- pgtable.h	11 Mar 2003 19:17:00 -0000	1.10
***************
*** 25,29 ****
  #include <linux/linkage.h>
  #include <linux/config.h>
- #include <linux/mm.h>
  
  
--- 25,28 ----
***************
*** 35,49 ****
  
  #if XTENSA_CACHE_ALIAS
-   /* We provide our own get_unmapped_area to avoid cache alias issue */
-   #define HAVE_ARCH_UNMAPPED_AREA
-   #define PG_mapped  PG_arch_1
  
!   /* this is a mask of the naughty bits that can cause cache aliasing
!    * problems.  Because xtensa has a configurable cache size we have to
!    * get funky.... Start with 0xffff_ffff and then mask off everything
!    * else that is not a problem...
!    */
!   #define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
!   #define XT_CACHE_ALIAS_BITS (( (-1) & ~(PAGE_SIZE-1)) & (XT_CACHE_WAYSIZE-1))
  #endif
  
--- 34,50 ----
  
  #if XTENSA_CACHE_ALIAS
  
! /* We provide our own get_unmapped_area to avoid cache alias issue */
! #define HAVE_ARCH_UNMAPPED_AREA
! #define PG_mapped  PG_arch_1
! 
! /* this is a mask of the naughty bits that can cause cache aliasing
!  * problems.  Because xtensa has a configurable cache size we have to
!  * get funky.... Start with 0xffff_ffff and then mask off everything
!  * else that is not a problem...
!  */
! #define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
! #define XT_CACHE_ALIAS_BITS (( (-1) & ~(PAGE_SIZE-1)) & (XT_CACHE_WAYSIZE-1))
! 
  #endif
  
***************
*** 83,95 ****
  
  /* 19feb2003 -- jn 
!  *   enabling dcache aliasing, have fear....
   */
  
  #if XTENSA_CACHE_ALIAS
!   void flush_dcache_page(struct page *page);
  //  void xtensa_cache_init(void);
  #else
!   #define flush_dcache_page(page)			do { } while (0)
! //  #define xtensa_cache_init()				do { } while (0)
  #endif
  
--- 84,97 ----
  
  /* 19feb2003 -- jn 
!  *   enabling dcache aliasing
   */
  
  #if XTENSA_CACHE_ALIAS
! void flush_dcache_page(struct page *page);
  //  void xtensa_cache_init(void);
+ 
  #else
! #define flush_dcache_page(page)			do { } while (0)
! //  #define xtensa_cache_init()			do { } while (0)
  #endif
  
***************
*** 98,113 ****
  #endif /* !defined (_LANGUAGE_ASSEMBLY) */
  
! /* Basically we have the same two-level (which is the logical three level
!  * Linux page table layout folded) page tables as the i386.
   */
  
! /* XTFIXME:  Need to pull the following constant from the CHAL, if possible. */
! #define WIRED_WAY_FOR_PAGE_TABLE  7
  
- /* 27feb2003 -- jn
-  *  I am hijacking way9 of the dtlb for the copy_user_page and clear_user_page
-  *  functions.
-  */
- #define WIRED_WAY_FOR_COPY_USER_PAGE 9
  
  
--- 100,126 ----
  #endif /* !defined (_LANGUAGE_ASSEMBLY) */
  
! /* Basically we have the same two-level (which is the logical three
!  * level Linux page table layout folded) page tables as the i386.  Use
!  * the first min-wired way for mapping page-table pages.  Page
!  * coloring requires a second min-wired way.
   */
  
! #if (XCHAL_DTLB_MINWIRED_SETS == 0)
! #error Need a min-wired way for mapping page-table pages
! #endif
! 
! #define _FIRST_MIN_WIRED  XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAY)
! #define _MIN_WIRED_COUNT  XCHAL_DTLB_SET(XCHAL_DTLB_MINWIRED_SET0, WAYS)
! 
! #define WIRED_WAY_FOR_PAGE_TABLE  _FIRST_MIN_WIRED
! 
! #if XTENSA_CACHE_ALIAS
! # if (_MIN_WIRED_COUNT >= 2)
! #  define WIRED_WAY_FOR_COPY_USER_PAGE  (_FIRST_MIN_WIRED + 1)
! # else
! #  error Page coloring requires its own min-wired dtlb way
! # endif
! #endif
  
  
  
***************
*** 131,156 ****
  #define FIRST_USER_PGD_NR	0
  
! /* 27feb2003 -- jn 
!  *  When caches are aliasable, we need to reserve a small portion of 
!  *  virtual space for copy_user_page, and clear_user_page.  This is 
!  *  used to reduce the amount of cache flushing required.
!  */
! 
! /*
!  * XTFIXME:  The CHAL should provide memory-map info on local memories and
!  * XLMI ports that are identity mapped.  They are typically located just
!  * below the kernel space at 0xD0000000, and they are relatively small
!  * (today).  We want to verify (with #error directives), however, that
!  * these memory-mapped processor features do not overlap the VMALLOC space
!  * we define here.  [Sep 11, 2002]
   */
  
- /* 0xC0000000-0xC8000000 reserved for vmalloc; below allows guard memory */
  #if (XTENSA_CACHE_ALIAS)
!     #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
!     #define XTENSA_ALIAS_RESERVE_START 0xC0010000
!     #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
  #else
!   #define VMALLOC_START 0xC0010000
  #endif
  
--- 144,163 ----
  #define FIRST_USER_PGD_NR	0
  
! /*  27feb2003 -- jn
!  *
!  *  0xC0000000-0xC8000000 reserved for kernel vmalloc.  See also
!  *  assume.h.  When caches are aliasable, we need to reserve a small
!  *  portion of virtual space for copy_user_page, and clear_user_page.
!  *  This is used to reduce the amount of cache flushing required.
   */
  
  #if (XTENSA_CACHE_ALIAS)
! 
! #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
! #define XTENSA_ALIAS_RESERVE_START 0xC0010000
! #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
! 
  #else
! #define VMALLOC_START 0xC0010000
  #endif
  
***************
*** 609,613 ****
  /* TLB operations. */
  
- /* XTFIXME: The following constants should come from the CHAL. */
  #define ITLB_WAYS_LOG2      XCHAL_ITLB_WAY_BITS
  #define DTLB_WAYS_LOG2      XCHAL_DTLB_WAY_BITS
--- 616,619 ----
***************
*** 662,665 ****
--- 668,690 ----
  			     "dsync\n\t"
  			     : : "a" (probe));
+ }
+ 
+ /* Use the .._no_isync functions with caution.  Generally, these are
+  * handy for bulk invalidates followed by a single 'isync'.  The
+  * caller must follow up with an 'isync', which can be relatively
+  * expensive on some Xtensa implementations. */
+ 
+ extern inline void invalidate_itlb_entry_no_isync (unsigned entry)
+ {
+ 	/* Caller must follow up with 'isync'. */
+ 	asm volatile ("iitlb  %0\n"
+ 		      : : "a" (entry) );
+ }
+ 
+ extern inline void invalidate_dtlb_entry_no_isync (unsigned entry)
+ {
+ 	/* Caller must follow up with 'isync'. */
+ 	asm volatile ("idtlb  %0\n"
+ 		      : : "a" (entry) );
  }