[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_be tie.h,NONE,1.1 core.h,1.3,1.4 def
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[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_be tie.h,NONE,1.1 core.h,1.3,1.4 defs.h,1.1,1.2 specreg.h,1.1,1.2 system.h,1.1,1.2
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From: <joe...@us...> - 2003-03-07 19:15:56
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Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be
In directory sc8-pr-cvs1:/tmp/cvs-serv31823/include/asm-xtensa/xtensa/config-linux_be
Modified Files:
core.h defs.h specreg.h system.h
Added Files:
tie.h
Log Message:
Update config-specific files with later versions. Removes the NSA/NSAU option from the baseline configs, corrects copyright info, and adds more macros to improve kernel implementation.
--- NEW FILE: tie.h ---
/*
* xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
*
* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
* It was generated for a specific Xtensa processor configuration,
* and furthermore for a specific set of TIE source files that extend
* basic core functionality.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* It is perfectly normal, however, for the HAL source itself to include this file.
*/
/*
* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2.1 of the GNU Lesser General Public
* License as published by the Free Software Foundation.
*
* This program is distributed in the hope that it would be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Further, this software is distributed without any warranty that it is
* free of the rightful claim of any third person regarding infringement
* or the like. Any license provided herein, whether implied or
* otherwise, applies only to this software file. Patent licenses, if
* any, provided herein do not apply to combinations of this program with
* other software, or any other product whatsoever.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this program; if not, write the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
#ifndef XTENSA_CONFIG_TIE_H
#define XTENSA_CONFIG_TIE_H
#include <xtensa/hal.h>
/*----------------------------------------------------------------------
GENERAL
----------------------------------------------------------------------*/
/*
* Separators for macros that expand into arrays.
* These can be predefined by files that #include this one,
* when different separators are required.
*/
/* Element separator for macros that expand into 1-dimensional arrays: */
#ifndef XCHAL_SEP
#define XCHAL_SEP ,
#endif
/* Array separator for macros that expand into 2-dimensional arrays: */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2 },{
#endif
/*----------------------------------------------------------------------
COPROCESSORS and EXTRA STATE
----------------------------------------------------------------------*/
#define XCHAL_CP_NUM 0 /* number of coprocessors */
#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
/* Space for coprocessors' state save areas: */
#define XCHAL_CP0_SA_SIZE 0
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP7_SA_SIZE 0
/* Minimum required alignments of CP state save areas: */
#define XCHAL_CP0_SA_ALIGN 1
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_ALIGN 1
/* Indexing macros: */
#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
/* Space for "extra" state (user special registers and non-cp TIE) save area: */
#define XCHAL_EXTRA_SA_SIZE 0
#define XCHAL_EXTRA_SA_ALIGN 1
/* Total save area size (extra + all coprocessors) */
/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
/* but included for Tor2 beta; doesn't account for alignment!): */
#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
/* Combined required alignment for all CP and EXTRA state save areas */
/* (does not include required alignment for any base config registers): */
#define XCHAL_CPEXTRA_SA_ALIGN 1
/* ... */
#ifdef _ASMLANGUAGE
/*
* Assembly-language specific definitions (assembly macros, etc.).
*/
#include <xtensa/config/specreg.h>
/********************
* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
*/
/* (none) */
/********************
* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
* (does not include zero-overhead loop registers and non-optional registers).
*/
/*
* Macro that expands to the body of a function that
* stores the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area in which to save extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_store_funcbody
.endm
/*
* Macro that expands to the body of a function that
* loads the extra (non-coprocessor) optional/custom state.
* Entry: a2 = ptr to save area from which to restore extra state
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_extra_load_funcbody
.endm
/********************
* Macros to save and restore the state of each TIE coprocessor.
*/
/********************
* Macros to create functions that save and restore the state of *any* TIE coprocessor.
*/
/*
* Macro that expands to the body of a function
* that stores the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area in which to save cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_store_funcbody
.endm
/*
* Macro that expands to the body of a function
* that loads the selected coprocessor's state (registers etc).
* Entry: a2 = ptr to save area from which to restore cp state
* a3 = coprocessor number
* Exit: any register a2-a15 (?) may have been clobbered.
*/
.macro xchal_cpi_load_funcbody
.endm
#endif /*_ASMLANGUAGE*/
/*
* Contents of save areas in terms of libdb register numbers.
* NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
* it is up to the user of this header file to define these macros
* usefully before each expansion of the CONTENTS_LIBDB macros.
* (Fields rsv[123] are reserved for future additions; they are currently
* set to zero but may be set to some useful values in the future.)
*
* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
*/
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#if 0 /* is there something equivalent for user TIE? */
#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
(CoreID) set in the Xtensa Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
#define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
#endif /*0*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
/* Misc instructions: */
#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#endif /*0*/
#endif /*XTENSA_CONFIG_TIE_H*/
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/core.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** core.h 7 Feb 2003 02:03:34 -0000 1.3
--- core.h 7 Mar 2003 19:15:16 -0000 1.4
***************
*** 1,24 ****
! /*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/core.h -- HAL definitions that are
! * dependent on CORE configuration.
! *
! * This header file is sometimes referred to as the "compile-time HAL"
! * or CHAL. It was generated for a specific Xtensa processor
! * configuration.
! *
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * It is perfectly normal, however, for the HAL source itself to
! * include this file.
*
! * This file is subject to the terms and conditions of the GNU General Public
! * License. See the file "COPYING" in the main directory of this archive
! * for more details.
*
! * Copyright (C) 1999 - 2003 Tensilica Inc.
*/
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
--- 1,38 ----
! /*
! * xtensa/config/core.h -- HAL definitions that are dependent on CORE configuration
*
! * This header file is sometimes referred to as the "compile-time HAL" or CHAL.
! * It was generated for a specific Xtensa processor configuration.
*
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * It is perfectly normal, however, for the HAL source itself to include this file.
! */
!
! /*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
+
#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H
***************
*** 435,439 ****
/*
! * Level-1 Exception Causes:
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
--- 449,455 ----
/*
! * General Exception Causes
! * (values of EXCCAUSE special register set by general exceptions,
! * which vector to the user, kernel, or double-exception vectors):
*/
#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction (IllegalInstruction) */
***************
*** 492,653 ****
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
- #define XCHAL_CP_NUM 0 /* number of coprocessors */
- #define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
- #define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
-
- /* Space for coprocessors' state save areas: */
- #define XCHAL_CP0_SA_SIZE 0
- #define XCHAL_CP1_SA_SIZE 0
- #define XCHAL_CP2_SA_SIZE 0
- #define XCHAL_CP3_SA_SIZE 0
- #define XCHAL_CP4_SA_SIZE 0
- #define XCHAL_CP5_SA_SIZE 0
- #define XCHAL_CP6_SA_SIZE 0
- #define XCHAL_CP7_SA_SIZE 0
- /* Minimum required alignments of CP state save areas: */
- #define XCHAL_CP0_SA_ALIGN 1
- #define XCHAL_CP1_SA_ALIGN 1
- #define XCHAL_CP2_SA_ALIGN 1
- #define XCHAL_CP3_SA_ALIGN 1
- #define XCHAL_CP4_SA_ALIGN 1
- #define XCHAL_CP5_SA_ALIGN 1
- #define XCHAL_CP6_SA_ALIGN 1
- #define XCHAL_CP7_SA_ALIGN 1
-
- /* Indexing macros: */
- #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
- #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
- #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
- #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
-
-
- /* Space for "extra" state (user special registers and non-cp TIE) save area: */
- #define XCHAL_EXTRA_SA_SIZE 0
- #define XCHAL_EXTRA_SA_ALIGN 1
-
- /* Total save area size (extra + all coprocessors) */
- /* (not useful until xthal_{save,restore}_all_extra() is implemented, */
- /* but included for Tor2 beta; doesn't account for alignment!): */
- #define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
-
- /* Combined required alignment for all CP and EXTRA state save areas */
- /* (does not include required alignment for any base config registers): */
- #define XCHAL_CPEXTRA_SA_ALIGN 1
-
- /* ... */
-
-
- #ifdef _ASMLANGUAGE
- /*
- * Assembly-language specific definitions (assembly macros, etc.).
- */
- #include <xtensa/config/specreg.h>
-
- /********************
- * Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
- */
-
- /* (none) */
-
-
- /********************
- * Macros to create functions that save and restore all EXTRA (non-coprocessor) state
- * (does not include zero-overhead loop registers and non-optional registers).
- */
-
- /*
- * Macro that expands to the body of a function that
- * stores the extra (non-coprocessor) optional/custom state.
- * Entry: a2 = ptr to save area in which to save extra state
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_extra_store_funcbody
- .endm
-
-
- /*
- * Macro that expands to the body of a function that
- * loads the extra (non-coprocessor) optional/custom state.
- * Entry: a2 = ptr to save area from which to restore extra state
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_extra_load_funcbody
- .endm
-
-
- /********************
- * Macros to save and restore the state of each TIE coprocessor.
- */
-
-
-
- /********************
- * Macros to create functions that save and restore the state of *any* TIE coprocessor.
- */
-
- /*
- * Macro that expands to the body of a function
- * that stores the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area in which to save cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_store_funcbody
- .endm
-
-
- /*
- * Macro that expands to the body of a function
- * that loads the selected coprocessor's state (registers etc).
- * Entry: a2 = ptr to save area from which to restore cp state
- * a3 = coprocessor number
- * Exit: any register a2-a15 (?) may have been clobbered.
- */
- .macro xchal_cpi_load_funcbody
- .endm
-
- #endif /*_ASMLANGUAGE*/
-
-
- /*
- * Contents of save areas in terms of libdb register numbers.
- * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
- * it is up to the user of this header file to define these macros
- * usefully before each expansion of the CONTENTS_LIBDB macros.
- * (Fields rsv[123] are reserved for future additions; they are currently
- * set to zero but may be set to some useful values in the future.)
- *
- * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
- * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
- * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
- */
-
- #define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
-
- #define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
! #define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
! #define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
- #define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
- #define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
--- 508,515 ----
#define XCHAL_HAVE_CP 0 /* 1 if coprocessor option configured (CPENABLE present) */
#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one (per cfg) */
! #include <xtensa/config/tie.h>
***************
*** 658,665 ****
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
! #define XCHAL_NUM_INSTRAM 1 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
! #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs configured */
! #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
--- 520,527 ----
#define XCHAL_NUM_INSTROM 0 /* number of core instruction ROMs configured */
! #define XCHAL_NUM_INSTRAM 0 /* number of core instruction RAMs configured */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs configured */
! #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs configured */
! #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports configured */
#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */
#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */
***************
*** 667,691 ****
#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */
- /* Instruction RAM 0: */
- #define XCHAL_INSTRAM0_VADDR 0xCFFFF000
- #define XCHAL_INSTRAM0_PADDR 0xCFFFF000
- #define XCHAL_INSTRAM0_SIZE 4096
- #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */
- #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */
- #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */
-
- /* Data RAM 0: */
- #define XCHAL_DATARAM0_VADDR 0xCFFFE000
- #define XCHAL_DATARAM0_PADDR 0xCFFFE000
- #define XCHAL_DATARAM0_SIZE 2048
- #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */
- #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */
- #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */
-
- /* XLMI Port 0: */
- #define XCHAL_XLMI0_VADDR 0xCFF80000
- #define XCHAL_XLMI0_PADDR 0xCFF80000
- #define XCHAL_XLMI0_SIZE 262144
-
--- 529,532 ----
***************
*** 796,802 ****
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
- */
! /* MMU okay: yes */
/*----------------------------------------------------------------------
--- 637,644 ----
fams: 0 / 6 / 18 / 1 / 2
fams: Bypass / Isolate / Cached / Exception / NACached
! MMU okay: yes
! */
!
/*----------------------------------------------------------------------
***************
*** 804,807 ****
--- 646,693 ----
----------------------------------------------------------------------*/
+ /*
+ * General notes on MMU parameters.
+ *
+ * Terminology:
+ * ASID = address-space ID (acts as an "extension" of virtual addresses)
+ * VPN = virtual page number
+ * PPN = physical page number
+ * CA = encoded cache attribute (access modes)
+ * TLB = translation look-aside buffer (term is stretched somewhat here)
+ * I = instruction (fetch accesses)
+ * D = data (load and store accesses)
+ * way = each TLB (ITLB and DTLB) consists of a number of "ways"
+ * that simultaneously match the virtual address of an access;
+ * a TLB successfully translates a virtual address if exactly
+ * one way matches the vaddr; if none match, it is a miss;
+ * if multiple match, one gets a "multihit" exception;
+ * each way can be independently configured in terms of number of
+ * entries, page sizes, which fields are writable or constant, etc.
+ * set = group of contiguous ways with exactly identical parameters
+ * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
+ * from the page table and storing it in one of the auto-refill ways;
+ * if this PTE load also misses, a miss exception is posted for s/w.
+ * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ * page arbitrarily under program control; it has a single entry,
+ * is non-auto-refill (some other way(s) must be auto-refill),
+ * all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ * restriction is that this be the only page size it supports).
+ *
+ * TLB way entries are virtually indexed.
+ * TLB ways that support multiple page sizes:
+ * - must have all writable VPN and PPN fields;
+ * - can only use one page size at any given time (eg. setup at startup),
+ * selected by the respective ITLBCFG or DTLBCFG special register,
+ * whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ * this list may be sparse for auto-refill ways because auto-refill
+ * ways have independent lists of supported page sizes sharing a
+ * common encoding with PTE entries; the encoding is the index into
+ * this list; unsupported sizes for a given way are zero in the list;
+ * selecting unsupported sizes results in undefined hardware behaviour;
+ * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
#define XCHAL_HAVE_CACHEATTR 0 /* 1 if CACHEATTR register present, 0 if TLBs present instead */
#define XCHAL_HAVE_TLBS 1 /* 1 if TLBs present, 0 if CACHEATTR present instead */
***************
*** 819,836 ****
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
! #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure */
! #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure */
- /* Instruction TLB: */
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
! #define XCHAL_ITLB_WAYS 7 /* number of ways */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
- /* Data TLB: */
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
! #define XCHAL_DTLB_WAYS 10 /* number of ways */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
- /* ... */
/*
--- 705,1022 ----
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
! #define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
! #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
!
!
! /*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
! #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
+ #define XCHAL_ITLB_SETS 4 /* number of sets (groups of ways with identical settings) */
+
+ /* Way set to which each way belongs: */
+ #define XCHAL_ITLB_WAY0_SET 0
+ #define XCHAL_ITLB_WAY1_SET 0
+ #define XCHAL_ITLB_WAY2_SET 0
+ #define XCHAL_ITLB_WAY3_SET 0
+ #define XCHAL_ITLB_WAY4_SET 1
+ #define XCHAL_ITLB_WAY5_SET 2
+ #define XCHAL_ITLB_WAY6_SET 3
+
+ /* Ways sets that are used by hardware auto-refill (ARF): */
+ #define XCHAL_ITLB_ARF_SETS 1 /* number of auto-refill sets */
+ #define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
+
+ /* Way sets that are "min-wired" (see terminology comment above): */
+ #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
+
+
+ /* ITLB way set 0 (group of ways 0 thru 3): */
+ #define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* ITLB way set 1 (group of ways 4 thru 4): */
+ #define XCHAL_ITLB_SET1_WAY 4 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* ITLB way set 2 (group of ways 5 thru 5): */
+ #define XCHAL_ITLB_SET2_WAY 5 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of ITLB way set 2 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_ASID_CONST 0x01
+ #define XCHAL_ITLB_SET2_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of ITLB way set 2 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_VPN_CONST 0xD0000000
+ #define XCHAL_ITLB_SET2_E1_VPN_CONST 0xD8000000
+ /* Constant PPN values for each entry of ITLB way set 2 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_PPN_CONST 0x00000000
+ #define XCHAL_ITLB_SET2_E1_PPN_CONST 0x00000000
+ /* Constant CA values for each entry of ITLB way set 2 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET2_E0_CA_CONST 0x07
+ #define XCHAL_ITLB_SET2_E1_CA_CONST 0x03
+
+ /* ITLB way set 3 (group of ways 6 thru 6): */
+ #define XCHAL_ITLB_SET3_WAY 6 /* index of first way in this way set */
+ #define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_ITLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_ITLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_ITLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
+ #define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_ITLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of ITLB way set 3 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_ASID_CONST 0x01
+ #define XCHAL_ITLB_SET3_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of ITLB way set 3 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_VPN_CONST 0xE0000000
+ #define XCHAL_ITLB_SET3_E1_VPN_CONST 0xF0000000
+ /* Constant PPN values for each entry of ITLB way set 3 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_PPN_CONST 0xF0000000
+ #define XCHAL_ITLB_SET3_E1_PPN_CONST 0xF0000000
+ /* Constant CA values for each entry of ITLB way set 3 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_ITLB_SET3_E0_CA_CONST 0x07
+ #define XCHAL_ITLB_SET3_E1_CA_CONST 0x03
+
+ /* Indexing macros: */
+ #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what
+ #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what )
+ #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what
+ #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what )
+ /*
+ * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+
+ /*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
! #define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
+ #define XCHAL_DTLB_SETS 5 /* number of sets (groups of ways with identical settings) */
+
+ /* Way set to which each way belongs: */
+ #define XCHAL_DTLB_WAY0_SET 0
+ #define XCHAL_DTLB_WAY1_SET 0
+ #define XCHAL_DTLB_WAY2_SET 0
+ #define XCHAL_DTLB_WAY3_SET 0
+ #define XCHAL_DTLB_WAY4_SET 1
+ #define XCHAL_DTLB_WAY5_SET 2
+ #define XCHAL_DTLB_WAY6_SET 3
+ #define XCHAL_DTLB_WAY7_SET 4
+ #define XCHAL_DTLB_WAY8_SET 4
+ #define XCHAL_DTLB_WAY9_SET 4
+
+ /* Ways sets that are used by hardware auto-refill (ARF): */
+ #define XCHAL_DTLB_ARF_SETS 1 /* number of auto-refill sets */
+ #define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
+
+ /* Way sets that are "min-wired" (see terminology comment above): */
+ #define XCHAL_DTLB_MINWIRED_SETS 1 /* number of "min-wired" sets */
+ #define XCHAL_DTLB_MINWIRED_SET0 4 /* index of n'th "min-wired" set */
+
+
+ /* DTLB way set 0 (group of ways 0 thru 3): */
+ #define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET0_WAYS 4 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* DTLB way set 1 (group of ways 4 thru 4): */
+ #define XCHAL_DTLB_SET1_WAY 4 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET1_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET1_PAGESIZES 4 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET1_PAGESZ_BITS 2 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* DTLB way set 2 (group of ways 5 thru 5): */
+ #define XCHAL_DTLB_SET2_WAY 5 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET2_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET2_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET2_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 27 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 27 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET2_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_VPN_CONSTMASK 0xF0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_PPN_CONSTMASK 0xF8000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of DTLB way set 2 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_ASID_CONST 0x01
+ #define XCHAL_DTLB_SET2_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of DTLB way set 2 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_VPN_CONST 0xD0000000
+ #define XCHAL_DTLB_SET2_E1_VPN_CONST 0xD8000000
+ /* Constant PPN values for each entry of DTLB way set 2 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_PPN_CONST 0x00000000
+ #define XCHAL_DTLB_SET2_E1_PPN_CONST 0x00000000
+ /* Constant CA values for each entry of DTLB way set 2 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET2_E0_CA_CONST 0x07
+ #define XCHAL_DTLB_SET2_E1_CA_CONST 0x03
+
+ /* DTLB way set 3 (group of ways 6 thru 6): */
+ #define XCHAL_DTLB_SET3_WAY 6 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET3_ENTRIES_LOG2 1 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET3_ENTRIES 2 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET3_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 28 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET3_ASID_CONSTMASK 0xFF /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_VPN_CONSTMASK 0xE0000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_PPN_CONSTMASK 0xF0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_CA_CONSTMASK 0x0000000F /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+ /* Constant ASID values for each entry of DTLB way set 3 (because ASID_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_ASID_CONST 0x01
+ #define XCHAL_DTLB_SET3_E1_ASID_CONST 0x01
+ /* Constant VPN values for each entry of DTLB way set 3 (because VPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_VPN_CONST 0xE0000000
+ #define XCHAL_DTLB_SET3_E1_VPN_CONST 0xF0000000
+ /* Constant PPN values for each entry of DTLB way set 3 (because PPN_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_PPN_CONST 0xF0000000
+ #define XCHAL_DTLB_SET3_E1_PPN_CONST 0xF0000000
+ /* Constant CA values for each entry of DTLB way set 3 (because CA_CONSTMASK is non-zero): */
+ #define XCHAL_DTLB_SET3_E0_CA_CONST 0x07
+ #define XCHAL_DTLB_SET3_E1_CA_CONST 0x03
+
+ /* DTLB way set 4 (group of ways 7 thru 9): */
+ #define XCHAL_DTLB_SET4_WAY 7 /* index of first way in this way set */
+ #define XCHAL_DTLB_SET4_WAYS 3 /* number of (contiguous) ways in this way set */
+ #define XCHAL_DTLB_SET4_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
+ #define XCHAL_DTLB_SET4_ENTRIES 1 /* number of entries in this way (always a power of 2) */
+ #define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+ #define XCHAL_DTLB_SET4_PAGESIZES 1 /* number of supported page sizes in this way */
+ #define XCHAL_DTLB_SET4_PAGESZ_BITS 0 /* number of bits to encode the page size */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
+ #define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
+ 2^PAGESZ_BITS entries in list, unsupported entries are zero */
+ #define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
+ #define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
+ #define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
+
+ /* Indexing macros: */
+ #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what
+ #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what )
+ #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what
+ #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what )
+ /*
+ * Example use: XCHAL_DTLB_SET(XCHAL_DTLB_ARF_SET0,ENTRIES)
+ * to get the value of XCHAL_DTLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
/*
***************
*** 877,885 ****
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00006700 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
! #define XCHAL_HW_CONFIGID0 0xC10FD3FF /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00806700 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
--- 1063,1071 ----
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
! #define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
***************
*** 1001,1008 ****
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
- #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
! #define XCHAL_HAVE_NSA 1 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
--- 1187,1193 ----
#define XCHAL_HAVE_DENSITY 1 /* 1 if density option configured, 0 otherwise */
#define XCHAL_HAVE_LOOPS 1 /* 1 if zero-overhead loops option configured, 0 otherwise */
/* Misc instructions: */
! #define XCHAL_HAVE_NSA 0 /* 1 if NSA/NSAU instructions option configured, 0 otherwise */
#define XCHAL_HAVE_MINMAX 0 /* 1 if MIN/MAX instructions option configured, 0 otherwise */
#define XCHAL_HAVE_SEXT 0 /* 1 if sign-extend instruction option configured, 0 otherwise */
***************
*** 1010,1024 ****
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
- #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
- #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
- #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
! #define XCHAL_HAVE_PRID 1 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
--- 1195,1212 ----
#define XCHAL_HAVE_MAC16 0 /* 1 if MAC16 option configured, 0 otherwise */
#define XCHAL_HAVE_MUL16 0 /* 1 if 16-bit integer multiply option configured, 0 otherwise */
/*#define XCHAL_HAVE_POPC 0*/ /* 1 if CRC instruction option configured, 0 otherwise */
/*#define XCHAL_HAVE_CRC 0*/ /* 1 if POPC instruction option configured, 0 otherwise */
#define XCHAL_HAVE_SPECULATION 0 /* 1 if speculation option configured, 0 otherwise */
/*#define XCHAL_HAVE_MP_SYNC 0*/ /* 1 if multiprocessor sync. option configured, 0 otherwise */
! #define XCHAL_HAVE_PRID 0 /* 1 if processor ID register configured, 0 otherwise */
#define XCHAL_NUM_MISC_REGS 2 /* number of miscellaneous registers (0..4) */
+
+ /* These relate a bit more to TIE: */
+ #define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
+ #define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
+ #define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
Index: defs.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/defs.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** defs.h 23 Oct 2002 20:53:21 -0000 1.1
--- defs.h 7 Mar 2003 19:15:17 -0000 1.2
***************
*** 1,18 ****
! #ifndef _XTENSA_BASE_HEADER
! #define _XTENSA_BASE_HEADER
/*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/defs.h -- Definitions for Xtensa
! * instructions, types, and protos.
! *
! * This file is subject to the terms and conditions of the GNU General Public
! * License. See the file "COPYING" in the main directory of this archive
! * for more details.
! *
! * Copyright (C) 2002 Tensilica Inc.
*/
#ifdef __XTENSA__
--- 1,32 ----
! /* Definitions for Xtensa instructions, types, and protos. */
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
+ /* Do not modify. This is automatically generated.*/
+
+ #ifndef _XTENSA_BASE_HEADER
+ #define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
***************
*** 206,234 ****
- #define NSA_ASM(arr, ars) {\
- __asm__ ("nsa %0, %1" : "=a" (arr) : "a" (ars)); \
- }
-
- #define XT_NSA(ars) \
- ({ \
- unsigned _arr; \
- int _ars = ars; \
- NSA_ASM(_arr, _ars); \
- _arr; \
- })
-
- #define NSAU_ASM(arr, ars) {\
- __asm__ ("nsau %0, %1" : "=a" (arr) : "a" (ars)); \
- }
-
- #define XT_NSAU(ars) \
- ({ \
- unsigned _arr; \
- unsigned _ars = ars; \
- NSAU_ASM(_arr, _ars); \
- _arr; \
- })
-
-
#endif /* __GNUC__ && !__XCC__ */
--- 220,223 ----
***************
*** 275,283 ****
#define XT_SSAI _TIE_SSAI
- /* Miscellaneous instructions */
- extern unsigned _TIE_NSA(int ars);
- extern unsigned _TIE_NSAU(unsigned ars);
- #define XT_NSA _TIE_NSA
- #define XT_NSAU _TIE_NSAU
#endif /* __XCC__ */
--- 264,267 ----
Index: specreg.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/specreg.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** specreg.h 23 Oct 2002 20:53:21 -0000 1.1
--- specreg.h 7 Mar 2003 19:15:18 -0000 1.2
***************
*** 1,18 ****
! #ifndef XTENSA_SPECREG_H
! #define XTENSA_SPECREG_H
/*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/specreg.h
! * Xtensa Special Register symbolic names.
! *
! * This file is subject to the terms and conditions of the GNU General Public
! * License. See the file "COPYING" in the main directory of this archive
! * for more details.
! *
! * Copyright (C) 2002 Tensilica Inc.
*/
/* Include these special register bitfield definitions, for historical reasons: */
--- 1,34 ----
! /*
! * Xtensa Special Register symbolic names
! */
!
! /* $Id$ */
/*
! * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
! *
! * This program is free software; you can redistribute it and/or modify
! * it under the terms of version 2.1 of the GNU Lesser General Public
! * License as published by the Free Software Foundation.
! *
! * This program is distributed in the hope that it would be useful, but
! * WITHOUT ANY WARRANTY; without even the implied warranty of
! * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
! *
! * Further, this software is distributed without any warranty that it is
! * free of the rightful claim of any third person regarding infringement
! * or the like. Any license provided herein, whether implied or
! * otherwise, applies only to this software file. Patent licenses, if
! * any, provided herein do not apply to combinations of this program with
! * other software, or any other product whatsoever.
! *
! * You should have received a copy of the GNU Lesser General Public
! * License along with this program; if not, write the Free Software
! * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
! * USA.
*/
+ #ifndef XTENSA_SPECREG_H
+ #define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
***************
*** 57,61 ****
#define DEBUGCAUSE 233
#define CCOUNT 234
- #define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
--- 73,76 ----
Index: system.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_be/system.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** system.h 23 Oct 2002 20:53:21 -0000 1.1
--- system.h 7 Mar 2003 19:15:18 -0000 1.2
***************
*** 1,25 ****
! #ifndef XTENSA_CONFIG_SYSTEM_H
! #define XTENSA_CONFIG_SYSTEM_H
/*
! * THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
! *
! * include/asm-xtensa/xtensa/config/system.h -- HAL definitions that
! * are dependent on SYSTEM configuration.
*
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * The HAL itself has historically included this file in some
! * instances, but this is not appropriate either because the HAL is
! * meant to be core-specific but system independent.
! *
! * This file is subject to the terms and conditions of the GNU General
! * Public License. See the file "COPYING" in the main directory of
! * this archive for more details.
! *
! * Copyright (C) 2002 Tensilica Inc.
*/
/*#include <xtensa/hal.h>*/
--- 1,42 ----
! /*
! * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
! *
! * NOTE: The location and contents of this file are highly subject to change.
! *
! * Source for configuration-independent binaries (which link in a
! * configuration-specific HAL library) must NEVER include this file.
! * The HAL itself has historically included this file in some instances,
! * but this is not appropriate either, because the HAL is meant to be
! * core-specific but system independent.
! */
/*
! * C...
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