[xtensa-cvscommit] linux/include/asm-xtensa assume.h,1.3,1.4 page.h,1.3,1.4 pgalloc.h,1.2,1.3 pgtabl
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[xtensa-cvscommit] linux/include/asm-xtensa assume.h,1.3,1.4 page.h,1.3,1.4 pgalloc.h,1.2,1.3 pgtable.h,1.7,1.8 shmparam.h,1.2,1.3
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From: <jn...@us...> - 2003-02-28 01:53:27
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Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv6560/include/asm-xtensa
Modified Files:
assume.h page.h pgalloc.h pgtable.h shmparam.h
Log Message:
Added support for caches that have "ways" larger than PAGE_SIZE.
This was mostly copied from the sh-4 port which suffers from the
same feature. There are still some optimizations that can be done
with regard to defering some cache flusing, and reducing some complete
cache flushes to flushes of the appropriate cache lines.
When the cache way size is less than or equal to PAGE_SIZE, all
of these changes should be optimized away, and the port should run
exactly as it did prior to these changes.
Index: assume.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/assume.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** assume.h 15 Feb 2003 02:02:40 -0000 1.3
--- assume.h 28 Feb 2003 01:53:10 -0000 1.4
***************
*** 49,52 ****
--- 49,56 ----
#endif
+ /* 20feb2003 -- jn
+ * cache aliasing is now being supported, have fear.
+ */
+ #if 0
#if XCHAL_ICACHE_SIZE > (XCHAL_ICACHE_WAYS * PAGE_SIZE)
#error Cache aliasing not supported.
***************
*** 55,58 ****
--- 59,63 ----
#if XCHAL_DCACHE_SIZE > (XCHAL_DCACHE_WAYS * PAGE_SIZE)
#error Cache aliasing not supported.
+ #endif
#endif
Index: page.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/page.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** page.h 15 Feb 2003 02:02:40 -0000 1.3
--- page.h 28 Feb 2003 01:53:10 -0000 1.4
***************
*** 19,22 ****
--- 19,23 ----
#include <xtensa/config/core.h>
+ #include <asm/xtutil.h>
/* PAGE_SHIFT determines the page size */
***************
*** 25,30 ****
--- 26,40 ----
#define PAGE_MASK (~(PAGE_SIZE-1))
+
+
#ifdef __KERNEL__
+ #define XCDCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
+ #if ( XCDCACHE_WAY_SIZE > PAGE_SIZE)
+ #define XTENSA_CACHE_ALIAS 1
+ #else
+ #define XTENSA_CACHE_ALIAS 0
+ #endif
+
#ifndef _LANGUAGE_ASSEMBLY
***************
*** 38,43 ****
#define clear_page(page) clear_page_asm (page)
#define copy_page(to, from) copy_page_asm (to, from)
! #define clear_user_page(page, vaddr) clear_page(page)
! #define copy_user_page(to, from, vaddr) copy_page(to, from)
/*
--- 48,65 ----
#define clear_page(page) clear_page_asm (page)
#define copy_page(to, from) copy_page_asm (to, from)
!
!
! /* 19feb2003 --jn
! * Some Xtensa's can have cache alias problems, for those we have to
! * use the magical copy and clear user page functions.
! */
!
! #if XTENSA_CACHE_ALIAS
! extern void clear_user_page(void *to, unsigned long addr);
! extern void copy_user_page(void *to, void *from, unsigned long addr);
! #else
! #define clear_user_page(page, vaddr) clear_page(page)
! #define copy_user_page(to, from, vaddr) copy_page(to, from)
! #endif
/*
Index: pgalloc.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgalloc.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** pgalloc.h 15 Feb 2003 02:02:40 -0000 1.2
--- pgalloc.h 28 Feb 2003 01:53:10 -0000 1.3
***************
*** 17,20 ****
--- 17,21 ----
#include <linux/config.h>
+ #include <linux/mm.h>
/* TLB flushing:
***************
*** 210,213 ****
--- 211,271 ----
#endif
}
+
+
+ static inline int ptep_test_and_clear_young(pte_t *ptep)
+ {
+ pte_t pte = *ptep;
+ if (!pte_young(pte))
+ return 0;
+ set_pte(ptep, pte_mkold(pte));
+ return 1;
+ }
+
+ static inline int ptep_test_and_clear_dirty(pte_t *ptep)
+ {
+ pte_t pte = *ptep;
+ if (!pte_dirty(pte))
+ return 0;
+ set_pte(ptep, pte_mkclean(pte));
+ return 1;
+ }
+
+ #if XTENSA_CACHE_ALIAS
+ static inline pte_t ptep_get_and_clear(pte_t *ptep)
+ {
+ pte_t pte = *ptep;
+ pte_clear(ptep);
+ if (!pte_present(pte)) {
+ struct page *page = pte_page(pte);
+ if (VALID_PAGE(page) &&
+ (!page->mapping || !(page->mapping->i_mmap_shared))) {
+ clear_bit(PG_mapped, &page->flags);
+ }
+ }
+ return pte;
+ }
+ #else
+ static inline pte_t ptep_get_and_clear(pte_t *ptep)
+ {
+ pte_t pte = *ptep;
+ pte_clear(ptep);
+ return pte;
+ }
+ #endif
+
+ static inline void ptep_set_wrprotect(pte_t *ptep)
+ {
+ pte_t old_pte = *ptep;
+ set_pte(ptep, pte_wrprotect(old_pte));
+ }
+
+ static inline void ptep_mkdirty(pte_t *ptep)
+ {
+ pte_t old_pte = *ptep;
+ set_pte(ptep, pte_mkdirty(old_pte));
+ }
+
+ #define pte_same(A,B) (pte_val(A) == pte_val(B))
+
#endif /* __ASM_XTENSA_PGALLOC_H */
Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** pgtable.h 15 Feb 2003 02:02:40 -0000 1.7
--- pgtable.h 28 Feb 2003 01:53:10 -0000 1.8
***************
*** 25,28 ****
--- 25,50 ----
#include <linux/linkage.h>
#include <linux/config.h>
+ #include <linux/mm.h>
+
+
+
+ /* If the xtensa configuration has a cache-way larger than the
+ * page size, then we have to provide our own get_unmapped_area
+ * function to attempt to prevent cache aliasing problems
+ */
+
+ #if XTENSA_CACHE_ALIAS
+ /* We provide our own get_unmapped_area to avoid cache alias issue */
+ #define HAVE_ARCH_UNMAPPED_AREA
+ #define PG_mapped PG_arch_1
+
+ /* this is a mask of the naughty bits that can cause cache aliasing
+ * problems. Because xtensa has a configurable cache size we have to
+ * get funky.... Start with 0xffff_ffff and then mask off everything
+ * else that is not a problem...
+ */
+ #define XT_CACHE_WAYSIZE (XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS)
+ #define XT_CACHE_ALIAS_BITS (( (-1) & ~(PAGE_SIZE-1)) & (XT_CACHE_WAYSIZE-1))
+ #endif
***************
*** 31,35 ****
*/
! #if XCHAL_DCACHE_IS_WRITEBACK
extern void flush_cache_all(void);
--- 53,57 ----
*/
! #if ((XCHAL_DCACHE_IS_WRITEBACK > 0) || (XTENSA_CACHE_ALIAS > 0))
extern void flush_cache_all(void);
***************
*** 42,51 ****
extern void flush_page_to_ram(struct page *page);
- /* dcache aliasing isn't a problem, so this can be null. */
- #define flush_dcache_page(page) do { } while (0)
#else
! #define flush_dcache_page(page) do { } while (0)
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
--- 64,71 ----
extern void flush_page_to_ram(struct page *page);
#else
! //#define flush_dcache_page(page) do { } while (0)
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
***************
*** 53,63 ****
#define flush_cache_page(vma,page) do { } while (0)
#define flush_cache_sigtramp(addr) do { } while (0)
#define flush_page_to_ram(page) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma, page) do { } while (0)
- #define flush_icache_user_range(vma, page, addr, len) do { } while (0)
#endif
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
--- 73,99 ----
#define flush_cache_page(vma,page) do { } while (0)
#define flush_cache_sigtramp(addr) do { } while (0)
+ #define flush_icache_user_range(vma, page, addr, len) do { } while (0)
+
#define flush_page_to_ram(page) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma, page) do { } while (0)
#endif
+
+ /* 19feb2003 -- jn
+ * enabling dcache aliasing, have fear....
+ */
+
+ #if XTENSA_CACHE_ALIAS
+ void flush_dcache_page(struct page *page);
+ // void xtensa_cache_init(void);
+ #else
+ #define flush_dcache_page(page) do { } while (0)
+ // #define xtensa_cache_init() do { } while (0)
+ #endif
+
+
+
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
***************
*** 69,72 ****
--- 105,115 ----
#define WIRED_WAY_FOR_PAGE_TABLE 7
+ /* 27feb2003 -- jn
+ * I am hijacking way9 of the dtlb for the copy_user_page and clear_user_page
+ * functions.
+ */
+ #define WIRED_WAY_FOR_COPY_USER_PAGE 9
+
+
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT 22
***************
*** 88,91 ****
--- 131,140 ----
#define FIRST_USER_PGD_NR 0
+ /* 27feb2003 -- jn
+ * When caches are aliasable, we need to reserve a small portion of
+ * virtual space for copy_user_page, and clear_user_page. This is
+ * used to reduce the amount of cache flushing required.
+ */
+
/*
* XTFIXME: The CHAL should provide memory-map info on local memories and
***************
*** 98,102 ****
/* 0xC0000000-0xC8000000 reserved for vmalloc; below allows guard memory */
! #define VMALLOC_START 0xC0010000
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END 0xC7FF0000
--- 147,158 ----
/* 0xC0000000-0xC8000000 reserved for vmalloc; below allows guard memory */
! #if (XTENSA_CACHE_ALIAS)
! #define XTENSA_ALIAS_RESERVE_SIZE XCDCACHE_WAY_SIZE
! #define XTENSA_ALIAS_RESERVE_START 0xC0010000
! #define VMALLOC_START (XTENSA_ALIAS_RESERVE_START + XTENSA_ALIAS_RESERVE_SIZE)
! #else
! #define VMALLOC_START 0xC0010000
! #endif
!
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END 0xC7FF0000
***************
*** 755,767 ****
* correct mapping. */
! extern inline void update_mmu_cache(struct vm_area_struct * vma,
! unsigned long address, pte_t pte)
! {
! invalidate_page_table();
! }
/* XTFIXME: Possible optimization opportunity here. */
! #include <asm-generic/pgtable.h>
--- 811,827 ----
* correct mapping. */
! extern void update_mmu_cache(struct vm_area_struct * vma,
! unsigned long address,
! pte_t pte);
/* XTFIXME: Possible optimization opportunity here. */
! //#include <asm-generic/pgtable.h>
! /* 27feb2003 jn
! * copied these into pgalloc.h to remove a circular
! * dependency.
! */
!
!
Index: shmparam.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/shmparam.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** shmparam.h 15 Feb 2003 02:02:40 -0000 1.2
--- shmparam.h 28 Feb 2003 01:53:10 -0000 1.3
***************
*** 10,15 ****
*/
- #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
#endif /* __ASM_XTENSA_SHMPARAM_H */
--- 10,32 ----
*/
+ #include <xtensa/config/core.h>
+ #include <asm/page.h>
+
+
+
+
+ /* 19feb2003 -- jn
+ *
+ * Xtensa can have variable size caches, and if
+ * the size of single way is larger than the page size,
+ * then we have to start worrying about cache aliasing
+ * problems (didn't they fix this problem like back in 1978?)
+ */
+ #if XTENSA_CACHE_ALIAS
+ #define SHMLBA XCDCACHE_WAY_SIZE
+ #else
+ #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
+ #endif
#endif /* __ASM_XTENSA_SHMPARAM_H */
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