[xtensa-cvscommit] linux/include/asm-xtensa processor.h,1.4,1.5

[<ma...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv1831

Modified Files:
	processor.h 
Log Message:
Remove dead/commented-out code from asm-xtensa/processor.h.



Index: processor.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/processor.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** processor.h	7 Feb 2003 02:03:34 -0000	1.4
--- processor.h	13 Feb 2003 22:25:20 -0000	1.5
***************
*** 69,82 ****
  #define current_text_addr() ({ void *pc; __asm__("movi	%0, 1f\n1:":"=r" (pc)); pc; })
  
- #if 0	/* unused */
- /*
-  *  CPU type and hardware bug flags. Kept separately for each CPU.
-  */
- enum cpu_type {
- 	CPU_T1040BE,
- 	CPU_T1040LE,
- 	CPU_XTENSA_NONE
- };
- #endif /*0*/
  
  struct xtensa_cpuinfo {
--- 69,72 ----
***************
*** 90,98 ****
  };
  
- #if XCHAL_EXTRA_SA_ALIGN < 16
- #define EXTRA_ALIGN   16
- #else
- #define EXTRA_ALIGN   XCHAL_EXTRA_SA_ALIGN
- #endif
  
  struct thread_struct {
--- 80,83 ----
***************
*** 126,171 ****
   */
  
! 	unsigned char* cpregs_ptr[XCHAL_CP_MAX];
  	/* Allocate storage for extra state and coprocessor state
  	 * (probably only needs XCHAL_EXTRA_SA_ALIGN alignment, but bigger alignment is safe). */
  	unsigned char cpextra[TOTAL_CPEXTRA_SIZE]
  		__attribute__ ((aligned(XCHAL_CPEXTRA_SA_ALIGN)));
- 	/*unsigned char extra[(XCHAL_EXTRA_SA_SIZE+15)&0xfffffff0]
- 		__attribute__ ((aligned(EXTRA_ALIGN)));*/
- 
- #if 0
- #if (XCHAL_CP_MASK & 1)
- #define __CP0SZ ((XCHAL_CP0_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp0_regs[__CP0SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 2)
- #define __CP1SZ ((XCHAL_CP1_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp1_regs[__CP1SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 4)
- #define __CP2SZ ((XCHAL_CP2_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp2_regs[__CP2SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 8)
- #define __CP3SZ ((XCHAL_CP3_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp3_regs[__CP3SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 16)
- #define __CP4SZ ((XCHAL_CP4_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp4_regs[__CP4SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 32)
- #define __CP5SZ ((XCHAL_CP5_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp5_regs[__CP5SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 64)
- #define __CP6SZ ((XCHAL_CP6_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp6_regs[__CP6SZ] __attribute__ ((aligned(16)));
- #endif
- #if (XCHAL_CP_MASK & 128)
- #define __CP7SZ ((XCHAL_CP7_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
- 	unsigned cp7_regs[__CP7SZ] __attribute__ ((aligned(16)));
- #endif
- #endif /*0*/
  
  };
--- 111,120 ----
   */
  
! 	unsigned char* cpregs_ptr[XCHAL_CP_MAX];	/* start of each CP save area within cpextra[] */
! 
  	/* Allocate storage for extra state and coprocessor state
  	 * (probably only needs XCHAL_EXTRA_SA_ALIGN alignment, but bigger alignment is safe). */
  	unsigned char cpextra[TOTAL_CPEXTRA_SIZE]
  		__attribute__ ((aligned(XCHAL_CPEXTRA_SA_ALIGN)));
  
  };