[xtensa-cvscommit] linux/include/asm-xtensa assume.h,1.1.1.1,1.2 mmu_context.h,1.2,1.3 pgtable.h,1.5,1.6

[<joe...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv7485/include/asm-xtensa

Modified Files:
	assume.h mmu_context.h pgtable.h 
Log Message:

XTFIXME cleanup.  Also, move a few system-wide architecture checks to a common location (assume.h).

Index: assume.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/assume.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** assume.h	28 Aug 2002 16:11:31 -0000	1.1.1.1
--- assume.h	13 Feb 2003 19:35:06 -0000	1.2
***************
*** 32,34 ****
--- 32,59 ----
  #endif
  
+ #if ( ! XCHAL_HAVE_INTERRUPTS)
+ #error What is Linux without interrupts?
+ #endif
+ 
+ #if XCHAL_ICACHE_SIZE > 0
+ # if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0
+ #  error cache configuration outside expected/supported range!
+ # endif
+ #endif
+ 
+ #if XCHAL_DCACHE_SIZE > 0
+ # if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0
+ #  error cache configuration outside expected/supported range!
+ # endif
+ #endif 
+ 
+ #if XCHAL_ICACHE_SIZE > (XCHAL_ICACHE_WAYS * PAGE_SIZE)
+ #error Cache aliasing not supported.
+ 
+ #endif
+ #if XCHAL_DCACHE_SIZE > (XCHAL_DCACHE_WAYS * PAGE_SIZE)
+ #error Cache aliasing not supported.
+ #endif
+ 
+  
  #endif /* __ASM_XTENSA_ATOMIC_H */

Index: mmu_context.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/mmu_context.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** mmu_context.h	20 Jan 2003 22:44:15 -0000	1.2
--- mmu_context.h	13 Feb 2003 19:35:06 -0000	1.3
***************
*** 29,55 ****
     same number and just uses NTLB_ENTRIES for both tlbs. */
  
! /* XTFIXME: We assume several things about the MMU here that are
!    really configurable, and the code should handle it as such.  We
!    need a more flexible method to handle this configurability.  We
!    should consider:
! 
!    o The number of indicies per way is configurable.
!    o Indicies are always consecutive and numbered from zero.
!    o The number of autorefill ways is configurable.
!    o The autorefill ways are not necessarily contiguous.
!    o The first autorefill way isn't necessarily way zero.
! 
!    Some ideas:
! 
!    Initialize an MMU data structure on startup that tells an accurate
!    picture of the MMU layout.  General functions would frequently
!    refer to this data structure.
! 
!    Provide an abundance of small, flexible, inline functions that will
!    do the required work correctly.  Beware of unwieldy source code
!    with too many #ifdef statements.
! 
!    [JET, 24 Jan 2002]
! */
  
  #define INDICIES_PER_ARF_WAY    4
--- 29,36 ----
     same number and just uses NTLB_ENTRIES for both tlbs. */
  
! /* XTFIXME: INDICES_PER_ARG_WAY is a parameter exposed on the GUI.
!    This information really should be available from the CHAL.  Current
!    values are either 4 or 8.  An incorrect setting results is simply
!    suboptimal, not incorrect. */
  
  #define INDICIES_PER_ARF_WAY    4
***************
*** 136,140 ****
  #endif
  
! #if (USER_RING == 0)
  #error The user and kernel rings really should not be equal.
  #endif
--- 117,121 ----
  #endif
  
! #if (USER_RING == KERNEL_RING)
  #error The user and kernel rings really should not be equal.
  #endif

Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** pgtable.h	17 Jan 2003 18:10:15 -0000	1.5
--- pgtable.h	13 Feb 2003 19:35:06 -0000	1.6
***************
*** 60,73 ****
  #endif
  
- 
- /* Check for cache aliasing, and kill the build if found. */
- 
- #if XCHAL_ICACHE_SIZE > (XCHAL_ICACHE_WAYS * PAGE_SIZE)
- #error Cache aliasing not supported.
- #endif
- #if XCHAL_DCACHE_SIZE > (XCHAL_DCACHE_WAYS * PAGE_SIZE)
- #error Cache aliasing not supported.
- #endif
- 
  #endif /* !defined (_LANGUAGE_ASSEMBLY) */
  
--- 60,63 ----