[xtensa-cvscommit] linux/arch/xtensa/kernel head.S,1.4,1.5

[<joe...@us...>]

Update of /cvsroot/xtensa/linux/arch/xtensa/kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv6141/arch/xtensa/kernel

Modified Files:
	head.S 
Log Message:

Replace cache invalidation code with equivalent, succinct assembler macros.  Also, some XTFIXME cleanup.

Index: head.S
===================================================================
RCS file: /cvsroot/xtensa/linux/arch/xtensa/kernel/head.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** head.S	29 Jan 2003 06:17:59 -0000	1.4
--- head.S	13 Feb 2003 19:32:02 -0000	1.5
***************
*** 26,30 ****
  #define _ASMLANGUAGE 1
  #define _LANGUAGE_ASSEMBLY 1
- #include <xtensa/config/specreg.h>
  #include <xtensa/cacheasm.h>
  #include <linux/config.h>
--- 26,29 ----
***************
*** 124,129 ****
  	movi	a0, 0
  
- /* XTFIXME:	Is there a CACHEATTR register here? */
- 
  #if XCHAL_HAVE_SPECULATION
  	wsr	a0, AV+0	// make all registers invalid
--- 123,126 ----
***************
*** 138,142 ****
  	wsr	a0, IBREAKENABLE
  	wsr	a0, ICOUNT
- 	/* XTFIXME: Hard-coded 15 below should come from the CHAL. */
  	movi	a0, 15
  	wsr	a0, ICOUNTLEVEL
--- 135,138 ----
***************
*** 189,195 ****
  #endif
  	rsync
- 
- #else /* XCHAL_HAVE_WINDOWED */
- #error Linux requires the Window Register Option
  #endif /* XCHAL_HAVE_WINDOWED */
  
--- 185,188 ----
***************
*** 303,352 ****
  	rsync
  
! 	/* XTFIXME: use macro invalidate_i{i|d}cache(a0, a7) */
! 
! #ifndef CYGPKG_HAL_XTENSA_CACHE_DEFINED
! 
! 	/*
! 	 *  Initialize the caches.
!          */
! 
! #if XCHAL_ICACHE_SIZE > 0
! #if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0
! #error cache configuration outside expected/supported range!
! #endif
!  
! 	movi	a0, 0
! 	movi	a7, XCHAL_ICACHE_SIZE / XCHAL_ICACHE_WAYS
! 1:	iii	a0, 0*XCHAL_ICACHE_LINESIZE
! 	iii	a0, 1*XCHAL_ICACHE_LINESIZE
! 	iii	a0, 2*XCHAL_ICACHE_LINESIZE
! 	iii	a0, 3*XCHAL_ICACHE_LINESIZE
! 	addi	a0, a0, 4*XCHAL_ICACHE_LINESIZE
! 	blt	a0, a7, 1b
!  
! 	isync
!  
! #endif                                                                        
! 
! #if XCHAL_DCACHE_SIZE > 0
! #if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0
! #error cache configuration outside expected/supported range!
! #endif
!  
! 	movi	a0, 0
! 	movi	a7, XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS
! 1:	dii	a0, 0*XCHAL_DCACHE_LINESIZE
! 	dii	a0, 1*XCHAL_DCACHE_LINESIZE
! 	dii	a0, 2*XCHAL_DCACHE_LINESIZE
! 	dii	a0, 3*XCHAL_DCACHE_LINESIZE
! 	addi	a0, a0, 4*XCHAL_DCACHE_LINESIZE
! 	blt	a0, a7, 1b
!  
! 	memw
! 	isync
! #endif
! 
! #endif /* CYGPKG_HAL_XTENSA_CACHE_DEFINED */
  
  	/*
           * Unpack some data
--- 296,307 ----
  	rsync
  
! 	/*  Initialize the caches.
! 	 *  Does not include flushing writeback d-cache.
! 	 *  a6, a7 are just working registers (clobbered).
! 	 */
  
+ 	icache_reset  a6, a7
+ 	dcache_reset  a6, a7
+ 	
  	/*
           * Unpack some data