[xtensa-cvscommit] linux/include/asm-xtensa cpextra.h,NONE,1.1 elf.h,1.4,1.5 processor.h,1.3,1.4 ptrace.h,1.7,1.8 sigcontext.h,1.1.1.1,1.2 user.h,1.1.1.1,1.2

[<ma...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv27017/include/asm-xtensa

Modified Files:
	elf.h processor.h ptrace.h sigcontext.h user.h 
Added Files:
	cpextra.h 
Log Message:
Implement TIE support in elf_fpregset_t for core dumps and ptrace.
The elf_fpregset_t contains coprocessor and non-coprocessor custom
state, as well as a table describing its layout for use by GDB.

Also add experimental traceback code on panic's (untested, but doesn't
break anything).



--- NEW FILE: cpextra.h ---
#ifndef _ASM_CPEXTRA_H
#define _ASM_CPEXTRA_H

/*
 * include/asm-xtensa/cpextra.h
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Tensilica Inc.
 */

#include <xtensa/config/core.h>

/*
 *  Maximum size in bytes of a contiguous collection of all
 *  custom state save areas (extra and coprocessor state for
 *  a given Xtensa processor configuration).
 *  Allows for all save areas to be minimally aligned
 *  for the CHAL save/restore sequences.
 */
#define TOTAL_CPEXTRA_SIZE	\
			( XCHAL_EXTRA_SA_SIZE + XCHAL_EXTRA_SA_ALIGN \
			+ XCHAL_CP0_SA_SIZE + XCHAL_CP0_SA_ALIGN \
			+ XCHAL_CP1_SA_SIZE + XCHAL_CP1_SA_ALIGN \
			+ XCHAL_CP2_SA_SIZE + XCHAL_CP2_SA_ALIGN \
			+ XCHAL_CP3_SA_SIZE + XCHAL_CP3_SA_ALIGN \
			+ XCHAL_CP4_SA_SIZE + XCHAL_CP4_SA_ALIGN \
			+ XCHAL_CP5_SA_SIZE + XCHAL_CP5_SA_ALIGN \
			+ XCHAL_CP6_SA_SIZE + XCHAL_CP6_SA_ALIGN \
			+ XCHAL_CP7_SA_SIZE + XCHAL_CP7_SA_ALIGN \
			+ 16		/* for possible end-alignment padding */ \
			)

#endif /* _ASM_CPEXTRA_H */

Index: elf.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/elf.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** elf.h	31 Jan 2003 04:37:19 -0000	1.4
--- elf.h	7 Feb 2003 02:03:34 -0000	1.5
***************
*** 11,17 ****
   * for more details.
   *
!  * Copyright (C) 2001 Tensilica Inc.
!  *	Authors:	Kevin Chea
!  *			Marc Gauthier
   *			Joe Taylor <jo...@te..., jo...@ya...>
   */
--- 11,18 ----
   * for more details.
   *
!  * Copyright (C) 2001 - 2003 Tensilica Inc.
!  *	Authors:	Christian Zankel <za...@te...> <ch...@za...>
!  *			Kevin Chea
!  *			Marc Gauthier <ma...@te...> <ma...@al...>
   *			Joe Taylor <jo...@te..., jo...@ya...>
   */
***************
*** 19,22 ****
--- 20,24 ----
  #include <asm/ptrace.h>
  #include <asm/page.h>
+ #include <asm/cpextra.h>
  #include <xtensa/config/core.h>
  
***************
*** 62,79 ****
  
  
! /* TOTAL_CP_SIZE is a byte count.  Round up ELF_NFPREG to the next
!  * 16-byte boundary.  Coprocessors are usually defined in TIE, and TIE
!  * load/stores can require 16-byte alignment. However, we do not need
!  * to ensure 16-byte alignment for each coprocessor's space here
!  * because we do not directly load/store coprocessor state to these
!  * data structures (see 'struct task_struct' definition in processor.h
!  * for that).  We use memcpy() to copy information over to here. */
  
- #define TOTAL_CP_SIZE  (XCHAL_CP0_SA_SIZE + XCHAL_CP1_SA_SIZE + \
- 			XCHAL_CP2_SA_SIZE + XCHAL_CP3_SA_SIZE + \
- 			XCHAL_CP4_SA_SIZE + XCHAL_CP5_SA_SIZE + \
- 			XCHAL_CP6_SA_SIZE + XCHAL_CP7_SA_SIZE)
  
! #define ELF_NFPREG	(((TOTAL_CP_SIZE + 15) & ~15) / sizeof(elf_fpreg_t))
  
  typedef double elf_fpreg_t;
--- 64,127 ----
  
  
! /*
!  *  Compute the size of the coprocessor & extra state layout (register info) table
!  *  (see arch/xtensa/kernel/cptable.S).
!  *  (Actually this is the maximum size of the table, as opposed to the actual size
!  *   which is available from the _xtensa_reginfo_table_size global variable.)
!  */
! #ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM
! # define XTENSA_CPE_LTABLE_SIZE	0	/* interim until all core.h's are updated */
! #else
! # define XTENSA_CPE_SEGMENT(num)	(num ? (1+num) : 0)	/* number of entries for a CP or extra */
! # define XTENSA_CPE_LTABLE_ENTRIES	\
! 		( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM) \
! 		+ XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM) \
! 		+ 1		/* final entry */	\
! 		)
! # define XTENSA_CPE_LTABLE_SIZE		(XTENSA_CPE_LTABLE_ENTRIES * 8)	/* in bytes */
! #endif /* defined(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) */
  
  
! /*
!  * Instantiations of the elf_fpregset_t type contain, in most
!  * architectures, the floating point (FPU) register set.
!  * For Xtensa, this type is extended to contain all custom state,
!  * ie. coprocessor and "extra" (non-coprocessor) state (including,
!  * for example, TIE-defined states and register files; as well
!  * as other optional processor state).
!  * This includes FPU state if a floating-point coprocessor happens
!  * to have been configured within the Xtensa processor.
!  *
!  * TOTAL_FPREGS_SIZE is the required size (without rounding)
!  * of elf_fpregset_t.  It provides space for the following:
!  *
!  *  a)	32-bit mask of active coprocessors for this task (similar
!  *	to CPENABLE in single-threaded Xtensa processor systems)
!  *
!  *  b)	table describing the layout of custom states (ie. of
!  *      individual registers, etc) within the save areas
!  *
!  *  c)  save areas for each coprocessor and for non-coprocessor
!  *      ("extra") state
!  *
!  * Note that save areas may require up to 16-byte alignment when
!  * accessed by save/restore sequences.  We do not need to ensure
!  * such alignment in an elf_fpregset_t structure because custom
!  * state is not directly loaded/stored into it; rather, save area
!  * contents are copied to elf_fpregset_t from the active save areas
!  * (see 'struct task_struct' definition in processor.h for that)
!  * using memcpy().  But we do allow space for such alignment,
!  * to allow optimizations of layout and copying.
!  */
! 
! #define TOTAL_FPREGS_SIZE	(4 + XTENSA_CPE_LTABLE_SIZE + TOTAL_CPEXTRA_SIZE)
! #define ELF_NFPREG	((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))
  
  typedef double elf_fpreg_t;

Index: processor.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/processor.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** processor.h	2 Dec 2002 22:15:03 -0000	1.3
--- processor.h	7 Feb 2003 02:03:34 -0000	1.4
***************
*** 9,15 ****
   * for more details.
   *
!  * Copyright (C) 2001 Tensilica Inc.
   *	Authors:	Joe Taylor <jo...@te..., jo...@ya...>
!  *			Marc Gauthier
   *			Kevin Chea
   */
--- 9,15 ----
   * for more details.
   *
!  * Copyright (C) 2001 - 2003 Tensilica Inc.
   *	Authors:	Joe Taylor <jo...@te..., jo...@ya...>
!  *			Marc Gauthier <ma...@te...> <ma...@al...>
   *			Kevin Chea
   */
***************
*** 17,23 ****
  
  /*
!  * User space process size: 1 GB.  Trampolining, which glibc uses for
!  * nested functions, requires all code to be in the same gigabyte of
!  * memory.
   */
  #define TASK_SIZE	0x40000000
--- 17,27 ----
  
  /*
!  * User space process size: 1 GB.
!  * Windowed call ABI requires caller and callee to
!  * be located within the same 1 GB region. 
!  * The C compiler places trampoline code on the stack
!  * for sources that take the address of a nested C function
!  * (a feature used by glibc), so the 1 GB requirement
!  * applies to the stack as well.
   */
  #define TASK_SIZE	0x40000000
***************
*** 30,33 ****
--- 34,38 ----
  #include <asm/ptrace.h>
  #include <asm/kstack.h>
+ #include <asm/cpextra.h>
  #include <xtensa/config/core.h>
  #include <linux/threads.h>
***************
*** 64,67 ****
--- 69,73 ----
  #define current_text_addr() ({ void *pc; __asm__("movi	%0, 1f\n1:":"=r" (pc)); pc; })
  
+ #if 0	/* unused */
  /*
   *  CPU type and hardware bug flags. Kept separately for each CPU.
***************
*** 72,75 ****
--- 78,82 ----
  	CPU_XTENSA_NONE
  };
+ #endif /*0*/
  
  struct xtensa_cpuinfo {
***************
*** 90,97 ****
  
  struct thread_struct {
- 	
- 	/* -16, because we always save the user's active window to the
- 	   kernel's exception stack frame. */
- 	unsigned long regfile[XCHAL_NUM_AREGS - 16];
  
  	unsigned long areg0;	/* kernel's a0 (return PC + window size) for context switching */
--- 97,100 ----
***************
*** 105,113 ****
  	unsigned long error_code;
  
! 	/* Allocate storage for extra state and coprocessor state. */
! 	unsigned char extra[(XCHAL_EXTRA_SA_SIZE+15)&0xfffffff0]
! 		__attribute__ ((aligned(EXTRA_ALIGN)));
! 	unsigned cpregs_ptr[XCHAL_CP_MAX];
  
  #if (XCHAL_CP_MASK & 1)
  #define __CP0SZ ((XCHAL_CP0_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
--- 108,138 ----
  	unsigned long error_code;
  
! 	/* -16, because we always save the user's active window to the
! 	   kernel's exception stack frame. */
! 	unsigned long regfile[XCHAL_NUM_AREGS - 16];
  
+ /*
+ #define XTOFS(last_start,last_size,align)	((last_start+last_size+align-1) & -align)
+ #define XTENSA_CPE_EXTRA_START	0
+ #define XTENSA_CPE_CP0_START	XTOFS(XTENSA_CPE_EXTRA_START, XCHAL_EXTRA_SA_SIZE, XCHAL_CP0_SA_ALIGN)
+ #define XTENSA_CPE_CP1_START	XTOFS(XTENSA_CPE_CP0_START, XCHAL_CP0_SA_SIZE, XCHAL_CP1_SA_ALIGN)
+ #define XTENSA_CPE_CP2_START	XTOFS(XTENSA_CPE_CP1_START, XCHAL_CP1_SA_SIZE, XCHAL_CP2_SA_ALIGN)
+ #define XTENSA_CPE_CP3_START	XTOFS(XTENSA_CPE_CP2_START, XCHAL_CP2_SA_SIZE, XCHAL_CP3_SA_ALIGN)
+ #define XTENSA_CPE_CP4_START	XTOFS(XTENSA_CPE_CP3_START, XCHAL_CP3_SA_SIZE, XCHAL_CP4_SA_ALIGN)
+ #define XTENSA_CPE_CP5_START	XTOFS(XTENSA_CPE_CP4_START, XCHAL_CP4_SA_SIZE, XCHAL_CP5_SA_ALIGN)
+ #define XTENSA_CPE_CP6_START	XTOFS(XTENSA_CPE_CP5_START, XCHAL_CP5_SA_SIZE, XCHAL_CP6_SA_ALIGN)
+ #define XTENSA_CPE_CP7_START	XTOFS(XTENSA_CPE_CP6_START, XCHAL_CP6_SA_SIZE, XCHAL_CP7_SA_ALIGN)
+ #define XTENSA_CPE_SIZE		XTOFS(XTENSA_CPE_CP7_START, XCHAL_CP7_SA_SIZE, 16)
+  */
+ 
+ 	unsigned char* cpregs_ptr[XCHAL_CP_MAX];
+ 	/* Allocate storage for extra state and coprocessor state
+ 	 * (probably only needs XCHAL_EXTRA_SA_ALIGN alignment, but bigger alignment is safe). */
+ 	unsigned char cpextra[TOTAL_CPEXTRA_SIZE]
+ 		__attribute__ ((aligned(XCHAL_CPEXTRA_SA_ALIGN)));
+ 	/*unsigned char extra[(XCHAL_EXTRA_SA_SIZE+15)&0xfffffff0]
+ 		__attribute__ ((aligned(EXTRA_ALIGN)));*/
+ 
+ #if 0
  #if (XCHAL_CP_MASK & 1)
  #define __CP0SZ ((XCHAL_CP0_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
***************
*** 142,146 ****
  	unsigned cp7_regs[__CP7SZ] __attribute__ ((aligned(16)));
  #endif
! 	
  };
  
--- 167,172 ----
  	unsigned cp7_regs[__CP7SZ] __attribute__ ((aligned(16)));
  #endif
! #endif /*0*/
! 
  };
  

Index: ptrace.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/ptrace.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** ptrace.h	30 Jan 2003 23:55:27 -0000	1.7
--- ptrace.h	7 Feb 2003 02:03:34 -0000	1.8
***************
*** 11,15 ****
   * Copyright (C) 2001 Tensilica Inc.
   *	Authors:	Joe Taylor <jo...@te..., jo...@ya...>
!  *			Marc Gauthier
   *			Kevin Chea
   */
--- 11,15 ----
   * Copyright (C) 2001 Tensilica Inc.
   *	Authors:	Joe Taylor <jo...@te..., jo...@ya...>
!  *			Marc Gauthier <ma...@te...> <ma...@al...>
   *			Kevin Chea
   */
***************
*** 111,114 ****
--- 111,115 ----
  #define PTRACE_GETFPREGS          14
  #define PTRACE_SETFPREGS          15
+ #define PTRACE_GETFPREGSIZE       18
  
  #ifndef __ASSEMBLY__

Index: sigcontext.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/sigcontext.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** sigcontext.h	28 Aug 2002 16:11:31 -0000	1.1.1.1
--- sigcontext.h	7 Feb 2003 02:03:34 -0000	1.2
***************
*** 10,14 ****
   *
   * Copyright (C) 2001 Tensilica Inc.
!  *	Authors:	Kevin Chea, Chris Songer, Marc Gauthier
   */
  
--- 10,15 ----
   *
   * Copyright (C) 2001 Tensilica Inc.
!  *	Authors:	Kevin Chea, Chris Songer,
!  *			Marc Gauthier <ma...@te...> <ma...@al...>
   */
  

Index: user.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/user.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** user.h	28 Aug 2002 16:11:31 -0000	1.1.1.1
--- user.h	7 Feb 2003 02:03:34 -0000	1.2
***************
*** 13,17 ****
   * Derived from SH.
   *
!  * Copyright (C) 2001 Tensilica Inc.
   */
  
--- 13,17 ----
   * Derived from SH.
   *
!  * Copyright (C) 2001 - 2003 Tensilica Inc.
   */
  
***************
*** 21,24 ****
--- 21,25 ----
  #include <asm/elf.h>
  
+ #if 0	/* not used for Xtensa? */
  /*
   * Core file format: The core file is written in such a way that gdb
***************
*** 44,56 ****
   */
  
- struct user_cp {
- 	elf_fpregset_t regs;
- };
- 
- /* Note that u_fpvalid is true for any coprocessor being used, not just an fpu. */
  struct user {
  	struct pt_regs	regs;			/* entire machine state */
! 	struct user_cp  cps;			/* co-processor registers  */
! 	int u_fpvalid;				/* True if co-processor(s) being used */
  	size_t		u_tsize;		/* text size (pages) */
  	size_t		u_dsize;		/* data size (pages) */
--- 45,52 ----
   */
  
  struct user {
  	struct pt_regs	regs;			/* entire machine state */
! 	elf_fpregset_t	cpregs;			/* coprocessor & extra registers  */
! 	unsigned	u_cpevalid;		/* non-zero if any coprocessor(s) or extra state used */
  	size_t		u_tsize;		/* text size (pages) */
  	size_t		u_dsize;		/* data size (pages) */
***************
*** 70,73 ****
--- 66,72 ----
  #define HOST_DATA_START_ADDR	(u.start_data)
  #define HOST_STACK_END_ADDR	(u.start_stack + u.u_ssize * NBPG)
+ 
+ #endif /*0*/
+ 
  
  #endif /* __ASM_XTENSA_USER_H */