[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_le core.h,1.2,1.3
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[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_le core.h,1.2,1.3
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From: <ma...@us...> - 2003-02-07 02:03:37
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Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le
In directory sc8-pr-cvs1:/tmp/cvs-serv27017/include/asm-xtensa/xtensa/config-linux_le
Modified Files:
core.h
Log Message:
Implement TIE support in elf_fpregset_t for core dumps and ptrace.
The elf_fpregset_t contains coprocessor and non-coprocessor custom
state, as well as a table describing its layout for use by GDB.
Also add experimental traceback code on panic's (untested, but doesn't
break anything).
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/core.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** core.h 28 Nov 2002 00:40:50 -0000 1.2
--- core.h 7 Feb 2003 02:03:34 -0000 1.3
***************
*** 11,15 ****
/*
! * Customer ID=40; Build=10966; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 11,15 ----
/*
! * Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
***************
*** 67,77 ****
----------------------------------------------------------------------*/
- /* XTFIXME: I disabled XCHAL_UNALIGNED_LOAD_EXCEPTION by adding an
- _XTFIXME suffix until I update all linux_be/linux_le configs to have
- unaligned exceptions. Do enable in software, simply remove the
- suffix. */
-
/* These apply to a selected set of core load and store instructions only (see ISA): */
! #define XCHAL_UNALIGNED_LOAD_EXCEPTION_XTFIXME 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
--- 67,72 ----
----------------------------------------------------------------------*/
/* These apply to a selected set of core load and store instructions only (see ISA): */
! #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
***************
*** 82,90 ****
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS 1 /* 1 if high-level interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
/* Masks of interrupts at each interrupt level: */
--- 77,94 ----
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* 1 if high-priority interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
#define XCHAL_HAVE_NMI 0 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
+ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels (not including level zero!) */
+ #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
+ #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
+ #define XCHAL_EXCM_LEVEL 1 /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
+ for XEA1, where there is no PS.EXCM, this is always 1;
+ interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
+ are termed "medium priority" interrupts (post T10xx only) */
+ /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
/* Masks of interrupts at each interrupt level: */
***************
*** 140,143 ****
--- 144,149 ----
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0x0001FFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0x0001FFFF
+ #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all low-priority interrupts */
+ #define XCHAL_EXCM_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
***************
*** 158,161 ****
--- 164,172 ----
0x0001FFFF
+ /* Interrupt numbers for each interrupt level at which only one interrupt was configured: */
+ /*#define XCHAL_INTLEVEL1_NUM ...more than one interrupt at this level...*/
+ /*#define XCHAL_INTLEVEL2_NUM ...more than one interrupt at this level...*/
+ /*#define XCHAL_INTLEVEL3_NUM ...more than one interrupt at this level...*/
+
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
***************
*** 332,336 ****
! /* External interrupt vectors/levels: */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
--- 343,354 ----
! /*
! * External interrupt vectors/levels.
! * These macros describe how Xtensa processor interrupt numbers
! * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
! * map to external BInterrupt<n> pins, for those interrupts
! * configured as external (level-triggered, edge-triggered, or NMI).
! * See the Xtensa processor databook for more details.
! */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
***************
*** 395,399 ****
#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
! #define XCHAL_KERNERL_VECTOR_PADDR 0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
--- 413,417 ----
#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
! #define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
***************
*** 427,431 ****
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
! #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT 9 /* Load or Store to Unaligned Address (LoadStoreAlignment) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
--- 445,449 ----
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
! #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store (Unaligned) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 592,595 ****
--- 610,655 ----
+ /*
+ * Contents of save areas in terms of libdb register numbers.
+ * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
+ * it is up to the user of this header file to define these macros
+ * usefully before each expansion of the CONTENTS_LIBDB macros.
+ * (Fields rsv[123] are reserved for future additions; they are currently
+ * set to zero but may be set to some useful values in the future.)
+ *
+ * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
+ * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
+ * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
+ */
+
+ #define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
+
+
+
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
***************
*** 816,831 ****
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00002AD6 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC10FD3FE /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00402AD6 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
! #define XCHAL_HW_RELEASE_MINOR 0 /* minor release of targeted hardware */
! #define XCHAL_HW_RELEASE_NAME "T1050.0" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
! #define XTHAL_HW_REL_T1050_0 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
--- 876,891 ----
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x000066FD /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC10FD3FE /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x008066FD /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
! #define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
! #define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
! #define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
***************
*** 977,980 ****
--- 1037,1079 ----
/* Belongs in xtensa/hal.h: */
#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
+
+
+ /*
+ * Because information as to exactly which hardware release is targeted
+ * by a given software build is not always available, compile-time HAL
+ * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
+ */
+ #ifndef XCHAL_HW_RELEASE_MAJOR
+ # define XCHAL_HW_CONFIGID_RELIABLE 0
+ #endif
+ #if XCHAL_HW_CONFIGID_RELIABLE
+ # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+ # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+ # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+ # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
+ #else
+ # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
+ : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
+ : XTHAL_MAYBE )
+ # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
+ : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
+ : XTHAL_MAYBE )
+ # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
+ ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
+ # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
+ #endif
+
+ /*
+ * Specific errata:
+ */
+
+ /*
+ * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
+ * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
+ */
+ #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
+ (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
+ || XCHAL_HW_RELEASE_AT(1050,0)))
+
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