[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_test core.h,1.3,1.4
Brought to you by:
zankel
Menu
▾
▴
[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_test core.h,1.3,1.4
|
From: <ma...@us...> - 2003-02-07 02:03:37
|
Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test
In directory sc8-pr-cvs1:/tmp/cvs-serv27017/include/asm-xtensa/xtensa/config
Modified Files:
core.h
Log Message:
Implement TIE support in elf_fpregset_t for core dumps and ptrace.
The elf_fpregset_t contains coprocessor and non-coprocessor custom
state, as well as a table describing its layout for use by GDB.
Also add experimental traceback code on panic's (untested, but doesn't
break anything).
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/core.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** core.h 17 Jan 2003 18:17:48 -0000 1.3
--- core.h 7 Feb 2003 02:03:34 -0000 1.4
***************
*** 11,15 ****
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 11,15 ----
/*
! * Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
***************
*** 420,424 ****
#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
! #define XCHAL_KERNERL_VECTOR_PADDR 0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
--- 420,424 ----
#define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR /* for backward compatibility */
! #define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
#define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
#define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR /* for backward compatibility */
***************
*** 460,464 ****
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
! #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT 9 /* Load or Store to Unaligned Address (LoadStoreAlignment) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
--- 460,464 ----
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
! #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store (Unaligned) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 1008,1011 ****
--- 1008,1135 ----
+ /*
+ * Contents of save areas in terms of libdb register numbers.
+ * NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
+ * it is up to the user of this header file to define these macros
+ * usefully before each expansion of the CONTENTS_LIBDB macros.
+ * (Fields rsv[123] are reserved for future additions; they are currently
+ * set to zero but may be set to some useful values in the future.)
+ *
+ * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
+ * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
+ * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
+ */
+
+ #define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 7
+ #define XCHAL_EXTRA_SA_CONTENTS_LIBDB \
+ CONTENTS_LIBDB_SREG(0x08000010, 0, 4, 4, 0, "ACCLO", 16, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_SREG(0x08000011, 4, 4, 4, 0, "ACCHI", 17, 0x000000FF, 0,0) \
+ CONTENTS_LIBDB_SREG(0x08000020, 8, 4, 4, 0, "MR0", 32, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_SREG(0x08000021, 12, 4, 4, 0, "MR1", 33, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_SREG(0x08000022, 16, 4, 4, 0, "MR2", 34, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_SREG(0x08000023, 20, 4, 4, 0, "MR3", 35, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_SREG(0x08000004, 24, 4, 4, 0, "BR", 4, 0x0000FFFF, 0,0) \
+ /* end */
+
+ #define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 18
+ #define XCHAL_CP0_SA_CONTENTS_LIBDB \
+ CONTENTS_LIBDB_UREG(0x0C0000E8, 0, 4, 4, 0, "FCR", 232, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_UREG(0x0C0000E9, 4, 4, 4, 0, "FSR", 233, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030000, 8, 4, 4, 0, "f0", 0, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030001, 12, 4, 4, 0, "f1", 1, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030002, 16, 4, 4, 0, "f2", 2, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030003, 20, 4, 4, 0, "f3", 3, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030004, 24, 4, 4, 0, "f4", 4, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030005, 28, 4, 4, 0, "f5", 5, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030006, 32, 4, 4, 0, "f6", 6, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030007, 36, 4, 4, 0, "f7", 7, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030008, 40, 4, 4, 0, "f8", 8, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10030009, 44, 4, 4, 0, "f9", 9, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1003000A, 48, 4, 4, 0, "f10", 10, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1003000B, 52, 4, 4, 0, "f11", 11, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1003000C, 56, 4, 4, 0, "f12", 12, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1003000D, 60, 4, 4, 0, "f13", 13, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1003000E, 64, 4, 4, 0, "f14", 14, 16, 4, "f", "FR", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1003000F, 68, 4, 4, 0, "f15", 15, 16, 4, "f", "FR", 0,0) \
+ /* end */
+
+ #define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 17
+ #define XCHAL_CP2_SA_CONTENTS_LIBDB \
+ CONTENTS_LIBDB_UREG(0x0C000001, 0, 4, 4, 0, "UR1", 1, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050000, 4, 4, 4, 0, "i320", 0, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050001, 8, 4, 4, 0, "i321", 1, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050002, 12, 4, 4, 0, "i322", 2, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050003, 16, 4, 4, 0, "i323", 3, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050004, 20, 4, 4, 0, "i324", 4, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050005, 24, 4, 4, 0, "i325", 5, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050006, 28, 4, 4, 0, "i326", 6, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050007, 32, 4, 4, 0, "i327", 7, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050008, 36, 4, 4, 0, "i328", 8, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10050009, 40, 4, 4, 0, "i329", 9, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1005000A, 44, 4, 4, 0, "i3210", 10, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1005000B, 48, 4, 4, 0, "i3211", 11, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1005000C, 52, 4, 4, 0, "i3212", 12, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1005000D, 56, 4, 4, 0, "i3213", 13, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1005000E, 60, 4, 4, 0, "i3214", 14, 16, 4, "i32", "i32", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1005000F, 64, 4, 4, 0, "i3215", 15, 16, 4, "i32", "i32", 0,0) \
+ /* end */
+
+ #define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
+
+ #define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 18
+ #define XCHAL_CP5_SA_CONTENTS_LIBDB \
+ CONTENTS_LIBDB_UREG(0x0C000002, 0, 4, 4, 0, "S64HI", 2, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_UREG(0x0C000003, 4, 4, 4, 0, "S64LO", 3, 0xFFFFFFFF, 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040000, 8, 8, 8, 0, "i640", 0, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040001, 16, 8, 8, 0, "i641", 1, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040002, 24, 8, 8, 0, "i642", 2, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040003, 32, 8, 8, 0, "i643", 3, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040004, 40, 8, 8, 0, "i644", 4, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040005, 48, 8, 8, 0, "i645", 5, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040006, 56, 8, 8, 0, "i646", 6, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040007, 64, 8, 8, 0, "i647", 7, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040008, 72, 8, 8, 0, "i648", 8, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10040009, 80, 8, 8, 0, "i649", 9, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1004000A, 88, 8, 8, 0, "i6410", 10, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1004000B, 96, 8, 8, 0, "i6411", 11, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1004000C, 104, 8, 8, 0, "i6412", 12, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1004000D, 112, 8, 8, 0, "i6413", 13, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1004000E, 120, 8, 8, 0, "i6414", 14, 16, 8, "i64", "i64", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1004000F, 128, 8, 8, 0, "i6415", 15, 16, 8, "i64", "i64", 0,0) \
+ /* end */
+
+ #define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 17
+ #define XCHAL_CP6_SA_CONTENTS_LIBDB \
+ CONTENTS_LIBDB_UREG(0x0C000000, 0, 4, 4, 0, "UR0", 0, 0x0000FFFF, 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060000, 4, 2, 2, 0, "i160", 0, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060001, 6, 2, 2, 0, "i161", 1, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060002, 8, 2, 2, 0, "i162", 2, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060003, 10, 2, 2, 0, "i163", 3, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060004, 12, 2, 2, 0, "i164", 4, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060005, 14, 2, 2, 0, "i165", 5, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060006, 16, 2, 2, 0, "i166", 6, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060007, 18, 2, 2, 0, "i167", 7, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060008, 20, 2, 2, 0, "i168", 8, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x10060009, 22, 2, 2, 0, "i169", 9, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1006000A, 24, 2, 2, 0, "i1610", 10, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1006000B, 26, 2, 2, 0, "i1611", 11, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1006000C, 28, 2, 2, 0, "i1612", 12, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1006000D, 30, 2, 2, 0, "i1613", 13, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1006000E, 32, 2, 2, 0, "i1614", 14, 16, 2, "i16", "i16", 0,0) \
+ CONTENTS_LIBDB_REGF(0x1006000F, 34, 2, 2, 0, "i1615", 15, 16, 2, "i16", "i16", 0,0) \
+ /* end */
+
+ #define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
+ #define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
+
+
+
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
***************
*** 1393,1396 ****
--- 1517,1559 ----
/* Belongs in xtensa/hal.h: */
#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */
+
+
+ /*
+ * Because information as to exactly which hardware release is targeted
+ * by a given software build is not always available, compile-time HAL
+ * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
+ */
+ #ifndef XCHAL_HW_RELEASE_MAJOR
+ # define XCHAL_HW_CONFIGID_RELIABLE 0
+ #endif
+ #if XCHAL_HW_CONFIGID_RELIABLE
+ # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+ # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+ # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_RELEASE_MAJOR,XCHAL_HW_RELEASE_MINOR, major,minor ) ? 1 : 0)
+ # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_RELEASE_MAJOR == (major)) ? 1 : 0)
+ #else
+ # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
+ : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
+ : XTHAL_MAYBE )
+ # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
+ : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
+ : XTHAL_MAYBE )
+ # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
+ ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
+ # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0)
+ #endif
+
+ /*
+ * Specific errata:
+ */
+
+ /*
+ * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
+ * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
+ */
+ #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \
+ (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
+ || XCHAL_HW_RELEASE_AT(1050,0)))
+
|
