[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_test core.h,1.2,1.3 defs.h,1.1,1.2 s
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[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_test core.h,1.2,1.3 defs.h,1.1,1.2 specreg.h,1.1,1.2 system.h,1.1,1.2
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From: <joe...@us...> - 2003-01-17 18:17:57
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Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test
In directory sc8-pr-cvs1:/tmp/cvs-serv30478
Modified Files:
core.h defs.h specreg.h system.h
Log Message:
Update config-specific files to reflect new linux_test config.
Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/core.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** core.h 28 Nov 2002 01:21:16 -0000 1.2
--- core.h 17 Jan 2003 18:17:48 -0000 1.3
***************
*** 11,15 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 11,15 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
***************
*** 64,82 ****
/*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS 1 /* 1 if high-level interrupt option configured, 0 otherwise */
#define XCHAL_HAVE_NMI 1 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero!) */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL0_MASK 0x00000000
! #define XCHAL_INTLEVEL1_MASK 0x0C44F022
! #define XCHAL_INTLEVEL2_MASK 0x120A0050
! #define XCHAL_INTLEVEL3_MASK 0x00000204
#define XCHAL_INTLEVEL4_MASK 0x81B00408
#define XCHAL_INTLEVEL5_MASK 0x60010901
--- 64,100 ----
/*----------------------------------------------------------------------
+ ADDRESS ALIGNMENT
+ ----------------------------------------------------------------------*/
+
+ /* These apply to a selected set of core load and store instructions only (see ISA): */
+ #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* 1 if unaligned loads cause an exception, 0 otherwise */
+ #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* 1 if unaligned stores cause an exception, 0 otherwise */
+
+
+ /*----------------------------------------------------------------------
INTERRUPTS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* 1 if interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* 1 if high-priority interrupt option configured, 0 otherwise */
! #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS
#define XCHAL_HAVE_NMI 1 /* 1 if NMI option configured, 0 otherwise */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
+ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* number of bits to hold an interrupt number: roundup(log2(number of interrupts)) */
#define XCHAL_NUM_EXTINTERRUPTS 10 /* number of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero!) */
+ #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */
+ #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */
+ #define XCHAL_EXCM_LEVEL 1 /* level of interrupts masked by PS.EXCM (XEA2 only; always 1 in T10xx);
+ for XEA1, where there is no PS.EXCM, this is always 1;
+ interrupts at levels FIRST_HIGHPRI <= n <= EXCM_LEVEL, if any,
+ are termed "medium priority" interrupts (post T10xx only) */
+ /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL0_MASK 0x00000000
! #define XCHAL_INTLEVEL1_MASK 0x0C04F222
! #define XCHAL_INTLEVEL2_MASK 0x124A0050
! #define XCHAL_INTLEVEL3_MASK 0x00000004
#define XCHAL_INTLEVEL4_MASK 0x81B00408
#define XCHAL_INTLEVEL5_MASK 0x60010901
***************
*** 93,99 ****
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
! 0x0C44F022 XCHAL_SEP \
! 0x120A0050 XCHAL_SEP \
! 0x00000204 XCHAL_SEP \
0x81B00408 XCHAL_SEP \
0x60010901 XCHAL_SEP \
--- 111,117 ----
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_MASKS 0x00000000 XCHAL_SEP \
! 0x0C04F222 XCHAL_SEP \
! 0x124A0050 XCHAL_SEP \
! 0x00000004 XCHAL_SEP \
0x81B00408 XCHAL_SEP \
0x60010901 XCHAL_SEP \
***************
*** 111,116 ****
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
! #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0C44F022
! #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x1E4EF072
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x1E4EF276
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x9FFEF67E
--- 129,134 ----
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000
! #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0C04F222
! #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x1E4EF272
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x1E4EF276
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x9FFEF67E
***************
*** 126,133 ****
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0xFFFFFFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0xFFFFFFFF
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
! 0x0C44F022 XCHAL_SEP \
! 0x1E4EF072 XCHAL_SEP \
0x1E4EF276 XCHAL_SEP \
0x9FFEF67E XCHAL_SEP \
--- 144,153 ----
#define XCHAL_INTLEVEL14_ANDBELOW_MASK 0xFFFFFFFF
#define XCHAL_INTLEVEL15_ANDBELOW_MASK 0xFFFFFFFF
+ #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all low-priority interrupts */
+ #define XCHAL_EXCM_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK /* mask of all interrupts masked by PS.EXCM (or CEXCM) */
/* As an array of entries (eg. for C constant arrays): */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS 0x00000000 XCHAL_SEP \
! 0x0C04F222 XCHAL_SEP \
! 0x1E4EF272 XCHAL_SEP \
0x1E4EF276 XCHAL_SEP \
0x9FFEF67E XCHAL_SEP \
***************
*** 144,147 ****
--- 164,175 ----
0xFFFFFFFF
+ /* Interrupt numbers for each interrupt level at which only one interrupt was configured: */
+ /*#define XCHAL_INTLEVEL1_NUM ...more than one interrupt at this level...*/
+ /*#define XCHAL_INTLEVEL2_NUM ...more than one interrupt at this level...*/
+ #define XCHAL_INTLEVEL3_NUM 2
+ /*#define XCHAL_INTLEVEL4_NUM ...more than one interrupt at this level...*/
+ /*#define XCHAL_INTLEVEL5_NUM ...more than one interrupt at this level...*/
+ #define XCHAL_INTLEVEL7_NUM 7
+
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 5
***************
*** 154,158 ****
#define XCHAL_INT7_LEVEL 7
#define XCHAL_INT8_LEVEL 5
! #define XCHAL_INT9_LEVEL 3
#define XCHAL_INT10_LEVEL 4
#define XCHAL_INT11_LEVEL 5
--- 182,186 ----
#define XCHAL_INT7_LEVEL 7
#define XCHAL_INT8_LEVEL 5
! #define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 4
#define XCHAL_INT11_LEVEL 5
***************
*** 167,171 ****
#define XCHAL_INT20_LEVEL 4
#define XCHAL_INT21_LEVEL 4
! #define XCHAL_INT22_LEVEL 1
#define XCHAL_INT23_LEVEL 4
#define XCHAL_INT24_LEVEL 4
--- 195,199 ----
#define XCHAL_INT20_LEVEL 4
#define XCHAL_INT21_LEVEL 4
! #define XCHAL_INT22_LEVEL 2
#define XCHAL_INT23_LEVEL 4
#define XCHAL_INT24_LEVEL 4
***************
*** 188,192 ****
7 XCHAL_SEP \
5 XCHAL_SEP \
! 3 XCHAL_SEP \
4 XCHAL_SEP \
5 XCHAL_SEP \
--- 216,220 ----
7 XCHAL_SEP \
5 XCHAL_SEP \
! 1 XCHAL_SEP \
4 XCHAL_SEP \
5 XCHAL_SEP \
***************
*** 201,205 ****
4 XCHAL_SEP \
4 XCHAL_SEP \
! 1 XCHAL_SEP \
4 XCHAL_SEP \
4 XCHAL_SEP \
--- 229,233 ----
4 XCHAL_SEP \
4 XCHAL_SEP \
! 2 XCHAL_SEP \
4 XCHAL_SEP \
4 XCHAL_SEP \
***************
*** 322,326 ****
! /* External interrupt vectors/levels: */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
--- 350,361 ----
! /*
! * External interrupt vectors/levels.
! * These macros describe how Xtensa processor interrupt numbers
! * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
! * map to external BInterrupt<n> pins, for those interrupts
! * configured as external (level-triggered, edge-triggered, or NMI).
! * See the Xtensa processor databook for more details.
! */
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
***************
*** 328,336 ****
#define XCHAL_EXTINT1_NUM 4 /* (intlevel 2) */
#define XCHAL_EXTINT2_NUM 7 /* (intlevel 7) */
! #define XCHAL_EXTINT3_NUM 9 /* (intlevel 3) */
#define XCHAL_EXTINT4_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 15 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 18 /* (intlevel 1) */
! #define XCHAL_EXTINT7_NUM 22 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 23 /* (intlevel 4) */
#define XCHAL_EXTINT9_NUM 30 /* (intlevel 5) */
--- 363,371 ----
#define XCHAL_EXTINT1_NUM 4 /* (intlevel 2) */
#define XCHAL_EXTINT2_NUM 7 /* (intlevel 7) */
! #define XCHAL_EXTINT3_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 15 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 18 /* (intlevel 1) */
! #define XCHAL_EXTINT7_NUM 22 /* (intlevel 2) */
#define XCHAL_EXTINT8_NUM 23 /* (intlevel 4) */
#define XCHAL_EXTINT9_NUM 30 /* (intlevel 5) */
***************
*** 352,360 ****
#define XCHAL_EXTINT1_LEVEL 2 /* (int number 4) */
#define XCHAL_EXTINT2_LEVEL 7 /* (int number 7) */
! #define XCHAL_EXTINT3_LEVEL 3 /* (int number 9) */
#define XCHAL_EXTINT4_LEVEL 1 /* (int number 13) */
#define XCHAL_EXTINT5_LEVEL 1 /* (int number 15) */
#define XCHAL_EXTINT6_LEVEL 1 /* (int number 18) */
! #define XCHAL_EXTINT7_LEVEL 1 /* (int number 22) */
#define XCHAL_EXTINT8_LEVEL 4 /* (int number 23) */
#define XCHAL_EXTINT9_LEVEL 5 /* (int number 30) */
--- 387,395 ----
#define XCHAL_EXTINT1_LEVEL 2 /* (int number 4) */
#define XCHAL_EXTINT2_LEVEL 7 /* (int number 7) */
! #define XCHAL_EXTINT3_LEVEL 1 /* (int number 9) */
#define XCHAL_EXTINT4_LEVEL 1 /* (int number 13) */
#define XCHAL_EXTINT5_LEVEL 1 /* (int number 15) */
#define XCHAL_EXTINT6_LEVEL 1 /* (int number 18) */
! #define XCHAL_EXTINT7_LEVEL 2 /* (int number 22) */
#define XCHAL_EXTINT8_LEVEL 4 /* (int number 23) */
#define XCHAL_EXTINT9_LEVEL 5 /* (int number 30) */
***************
*** 425,428 ****
--- 460,464 ----
#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation (Speculation) */
#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction (Privileged) */
+ #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT 9 /* Load or Store to Unaligned Address (LoadStoreAlignment) */
#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception (ITlbMiss) */
#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 1196,1211 ****
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x00002BC6 /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC1FFDFFE /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x00402BC6 /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
! #define XCHAL_HW_RELEASE_MINOR 0 /* minor release of targeted hardware */
! #define XCHAL_HW_RELEASE_NAME "T1050.0" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
! #define XTHAL_HW_REL_T1050_0 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
--- 1232,1247 ----
(CoreID) set in the Xtensa Processor Generator */
! #define XCHAL_BUILD_UNIQUE_ID 0x000063EB /* software build-unique ID (22-bit) */
/* These definitions describe the hardware targeted by this software: */
#define XCHAL_HW_CONFIGID0 0xC1FFDFFE /* config ID reg 0 value (upper 32 of 64 bits) */
! #define XCHAL_HW_CONFIGID1 0x008063EB /* config ID reg 1 value (lower 32 of 64 bits) */
#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
! #define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
! #define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
#define XTHAL_HW_REL_T1050 1
! #define XTHAL_HW_REL_T1050_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
Index: defs.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/defs.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** defs.h 23 Oct 2002 20:53:21 -0000 1.1
--- defs.h 17 Jan 2003 18:17:49 -0000 1.2
***************
*** 2,6 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 2,6 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
Index: specreg.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/specreg.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** specreg.h 23 Oct 2002 20:53:21 -0000 1.1
--- specreg.h 17 Jan 2003 18:17:50 -0000 1.2
***************
*** 6,10 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 6,10 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
Index: system.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_test/system.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** system.h 23 Oct 2002 20:53:21 -0000 1.1
--- system.h 17 Jan 2003 18:17:50 -0000 1.2
***************
*** 12,16 ****
/*
! * Customer ID=40; Build=11206; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
--- 12,16 ----
/*
! * Customer ID=40; Build=25579; Copyright (c) 2002 by Tensilica Inc. ALL RIGHTS RESERVED.
* These coded instructions, statements, and computer programs are the
* copyrighted works and confidential proprietary information of Tensilica Inc.
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