[xtensa-cvscommit] linux/include/asm-xtensa pgtable.h,1.3,1.4

[<joe...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv4681/include/asm-xtensa

Modified Files:
	pgtable.h 
Log Message:

Add support for writeback caches.  Affects only linux_test config.


Index: pgtable.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/pgtable.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** pgtable.h	29 Oct 2002 01:20:33 -0000	1.3
--- pgtable.h	17 Jan 2003 00:31:30 -0000	1.4
***************
*** 27,68 ****
  
  
! /* With physically tagged caches and appropriately sized caches (to
!  * avoid aliasing problems), caches do not need flushing at all.  This
!  * limitation is imposed on Xtensa Processors intending to run Linux.
!  * Those using Xtensa Processors with potential aliasing problems must
!  * rethink these macros.
   */
  
! /* XTFIXME: Perhaps a #error statement would be useful here.  The
!  * condition would be based on constants from the CHAL, and would
!  * detect potential aliasing problems.
!  */
  
! #define flush_dcache_page(page)	        do { } while (0)
! #define flush_cache_all()		do { } while (0)
! #define flush_cache_mm(mm)		do { } while (0)
! #define flush_cache_range(mm,start,end)	do { } while (0)
! #define flush_cache_page(vma,page)	do { } while (0)
! #define flush_cache_sigtramp(addr)	do { } while (0)
! #define flush_page_to_ram(page)		do { } while (0)
! #define flush_icache_range(start, end)	flush_cache_all()
! #define flush_icache_page(vma, page)	do { } while (0)
  #define flush_icache_user_range(vma, page, addr, len)	do { } while (0)
  
! #define invalidate_dcache_range(start, end) 				\
!   do {									\
! 	unsigned long v = (unsigned long)start & ~(XCHAL_DCACHE_LINESIZE - 1);		\
! 	asm ("99: dhi %0, 0\n\r"					\
! 	     "    addi %0, %0, " XTSTR(XCHAL_DCACHE_LINESIZE) "\n\r"	\
! 	     "    blt %0, %1, 99b\n\r" : "+r" (v) : "r" (end));	\
!   } while (0)
  
  
  /* Basically we have the same two-level (which is the logical three level
   * Linux page table layout folded) page tables as the i386.
   */
  
- #endif /* !defined (_LANGUAGE_ASSEMBLY) */
- 
  /* XTFIXME:  Need to pull the following constant from the CHAL, if possible. */
  #define WIRED_WAY_FOR_PAGE_TABLE  7
--- 27,79 ----
  
  
! /* Only if the dcache is writeback do we still need to flush at
!  * times. Cache aliasing is not allowed (yet) and not supported (yet).
   */
  
! #if XCHAL_DCACHE_IS_WRITEBACK
  
! extern void flush_cache_all(void);
! extern void flush_cache_mm(struct mm_struct *mm);
! extern void flush_cache_range(struct mm_struct *mm, unsigned long start,
! 				 unsigned long end);
! extern void flush_cache_page(struct vm_area_struct *vma, unsigned long page);
! extern void flush_icache_range(unsigned long start, unsigned long end);
! extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
! extern void flush_page_to_ram(struct page *page);
! 
! /* dcache aliasing isn't a problem, so this can be null. */
! #define flush_dcache_page(page)				do { } while (0)
! 
! #else
! 
! #define flush_dcache_page(page)				do { } while (0)
! #define flush_cache_all()				do { } while (0)
! #define flush_cache_mm(mm)				do { } while (0)
! #define flush_cache_range(mm,start,end)			do { } while (0)
! #define flush_cache_page(vma,page)			do { } while (0)
! #define flush_cache_sigtramp(addr)			do { } while (0)
! #define flush_page_to_ram(page)				do { } while (0)
! #define flush_icache_range(start, end)			do { } while (0)
! #define flush_icache_page(vma, page)			do { } while (0)
  #define flush_icache_user_range(vma, page, addr, len)	do { } while (0)
  
! #endif
  
  
+ /* Check for cache aliasing, and kill the build if found. */
+ 
+ #if (XCHAL_ICACHE_WAYS * PAGE_SIZE) > XCHAL_ICACHE_SIZE
+ #error Cache aliasing not supported.
+ #endif
+ #if (XCHAL_DCACHE_WAYS * PAGE_SIZE) > XCHAL_DCACHE_SIZE
+ #error Cache aliasing not supported.
+ #endif
+ 
+ #endif /* !defined (_LANGUAGE_ASSEMBLY) */
+ 
  /* Basically we have the same two-level (which is the logical three level
   * Linux page table layout folded) page tables as the i386.
   */
  
  /* XTFIXME:  Need to pull the following constant from the CHAL, if possible. */
  #define WIRED_WAY_FOR_PAGE_TABLE  7
***************
*** 743,750 ****
  }
  
- 
- /* The document "Linux Cache Flush Architecture" offers hints on
-  * function update_mmu_cache, but it's misleading for Xtensa
-  * processors. */
  
  /* The kernel (in mm/memory.c) often invokes this macro when a page
--- 754,757 ----