[xtensa-cvscommit] linux/include/asm-xtensa processor.h,1.2,1.3

[<joe...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa
In directory sc8-pr-cvs1:/tmp/cvs-serv12851/include/asm-xtensa

Modified Files:
	processor.h 
Log Message:

Fix a structure that assumed config sizes were defined in words instead of bytes.  The CHAL always defines sizes in bytes.


Index: processor.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/processor.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** processor.h	1 Nov 2002 20:08:53 -0000	1.2
--- processor.h	2 Dec 2002 22:15:03 -0000	1.3
***************
*** 111,136 ****
  
  #if (XCHAL_CP_MASK & 1)
! 	unsigned cp0_regs[XCHAL_CP0_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 2)
! 	unsigned cp1_regs[XCHAL_CP1_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 4)
! 	unsigned cp2_regs[XCHAL_CP2_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 8)
! 	unsigned cp3_regs[XCHAL_CP3_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 16)
! 	unsigned cp4_regs[XCHAL_CP4_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 32)
! 	unsigned cp5_regs[XCHAL_CP5_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 64)
! 	unsigned cp6_regs[XCHAL_CP6_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 128)
! 	unsigned cp7_regs[XCHAL_CP7_SA_SIZE] __attribute__ ((aligned(16)));
  #endif
  	
--- 111,144 ----
  
  #if (XCHAL_CP_MASK & 1)
! #define __CP0SZ ((XCHAL_CP0_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp0_regs[__CP0SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 2)
! #define __CP1SZ ((XCHAL_CP1_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp1_regs[__CP1SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 4)
! #define __CP2SZ ((XCHAL_CP2_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp2_regs[__CP2SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 8)
! #define __CP3SZ ((XCHAL_CP3_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp3_regs[__CP3SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 16)
! #define __CP4SZ ((XCHAL_CP4_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp4_regs[__CP4SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 32)
! #define __CP5SZ ((XCHAL_CP5_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp5_regs[__CP5SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 64)
! #define __CP6SZ ((XCHAL_CP6_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp6_regs[__CP6SZ] __attribute__ ((aligned(16)));
  #endif
  #if (XCHAL_CP_MASK & 128)
! #define __CP7SZ ((XCHAL_CP7_SA_SIZE + sizeof(unsigned) -1) / sizeof(unsigned))
! 	unsigned cp7_regs[__CP7SZ] __attribute__ ((aligned(16)));
  #endif