[xtensa-cvscommit] linux/include/asm-xtensa/xtensa/config-linux_le core.h,1.1,1.2

[<joe...@us...>]

Update of /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le
In directory sc8-pr-cvs1:/tmp/cvs-serv11618/include/asm-xtensa/xtensa/config-linux_le

Modified Files:
	core.h 
Log Message:

Add unaligned exception handling.  None of this code is on by default, and we'll leave it off until we sync up with hardware that supports this exception.  See the XTFIXME comment in the core.h files to enable this code.


Index: core.h
===================================================================
RCS file: /cvsroot/xtensa/linux/include/asm-xtensa/xtensa/config-linux_le/core.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** core.h	23 Oct 2002 20:53:21 -0000	1.1
--- core.h	28 Nov 2002 00:40:50 -0000	1.2
***************
*** 64,67 ****
--- 64,81 ----
  
  /*----------------------------------------------------------------------
+ 				ADDRESS ALIGNMENT
+   ----------------------------------------------------------------------*/
+ 
+ /* XTFIXME: I disabled XCHAL_UNALIGNED_LOAD_EXCEPTION by adding an
+    _XTFIXME suffix until I update all linux_be/linux_le configs to have
+    unaligned exceptions.  Do enable in software, simply remove the
+    suffix. */
+ 
+ /*  These apply to a selected set of core load and store instructions only (see ISA):  */
+ #define XCHAL_UNALIGNED_LOAD_EXCEPTION_XTFIXME	1	/* 1 if unaligned loads cause an exception, 0 otherwise */
+ #define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* 1 if unaligned stores cause an exception, 0 otherwise */
+ 
+ 
+ /*----------------------------------------------------------------------
  				INTERRUPTS
    ----------------------------------------------------------------------*/
***************
*** 413,416 ****
--- 427,431 ----
  #define XCHAL_EXCCAUSE_SPECULATION			7	/* Speculation (Speculation) */
  #define XCHAL_EXCCAUSE_PRIVILEGED			8	/* Privileged Instruction (Privileged) */
+ #define XCHAL_EXCCAUSE_LOAD_STORE_ALIGNMENT		9	/* Load or Store to Unaligned Address (LoadStoreAlignment) */
  #define XCHAL_EXCCAUSE_ITLB_MISS			16	/* ITlb Miss Exception (ITlbMiss) */
  #define XCHAL_EXCCAUSE_ITLB_MULTIHIT			17	/* ITlb Mutltihit Exception (ITlbMultihit) */
***************
*** 797,800 ****
--- 812,818 ----
  
  #define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* number of write buffer entries */
+ 
+ #define XCHAL_CORE_ID			"linux_le"	/* configuration's alphanumeric core identifier
+ 							   (CoreID) set in the Xtensa Processor Generator */
  
  #define XCHAL_BUILD_UNIQUE_ID		0x00002AD6	/* software build-unique ID (22-bit) */