[xtensa-cvscommit] linux/Documentation Configure.help,1.1.1.1,1.2
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From: <joe...@us...> - 2002-10-25 20:52:20
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Update of /cvsroot/xtensa/linux/Documentation
In directory usw-pr-cvs1:/tmp/cvs-serv31294/Documentation
Modified Files:
Configure.help
Log Message:
Add some 'help' text for Xtensa-specific kernel configuration options.
Index: Configure.help
===================================================================
RCS file: /cvsroot/xtensa/linux/Documentation/Configure.help,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** Configure.help 28 Aug 2002 16:09:52 -0000 1.1.1.1
--- Configure.help 25 Oct 2002 20:52:16 -0000 1.2
***************
*** 234,237 ****
--- 234,298 ----
Axis Communication site, <http://developer.axis.com/>.
+ Tensilica Xtensa processors
+ CONFIG_XTENSA
+ Xtensa processors are 32-bit RISC machines designed by Tensilica
+ primarily for embedded systems. These processors are both
+ configurable and extensible. The Linux port supports all processor
+ configurations and extensions, with reasonable minimum requirements.
+ The Xtensa Linux project has a home page at
+ <http://xtensa.sourceforge.net/>.
+
+ Xtensa processor configuration
+ CONFIG_XTENSA_CONFIG_LINUX_BE
+ The linux_be processor configuration is a base Xtensa config
+ supported in MontaVista Linux distributions. It contains no TIE,
+ no coprocessors, and the following configuration options:
+
+ Code Density Option 2 Misc Special Registers
+ NSA/NSAU Instructions 128-bit Data Bus Width
+ Processor ID 8K, 2-way I and D Caches
+ Zero-Overhead Loops 2 Inst Address Break Registers
+ Big Endian 2 Data Address Break Registers
+ 64 General-Purpose Registers JTAG Interface and Trace Port
+ 17 Interrupts MMU w/ TLBs and Autorefill
+ 3 Interrupt Levels 8 Autorefill Ways (I/D TLBs)
+ 3 Timers
+
+ The linux_le processor configuration is the same as linux_be,
+ except that it is little endian.
+
+ The linux_test processor configuration is designed for internal
+ testing only. It is probably not suitable for production systems.
+
+ Your processor configuration must match exactly to what you select
+ here. You can manually add your configuration (search the source
+ tree for "CONFIG_XTENSA_CONFIG_LINUX_BE") or use Tensilica's
+ script to install an overlay automatically for your processor
+ configuration.
+
+ Xtensa system type
+ CONFIG_XTENSA_PLATFORM_ISS
+ ISS is an acronym for Tensilica's Instruction Set Simulator. As of
+ this writing, ISS can be used to boot Linux and even run simple
+ user tasks in a ramdisk. While extremely useful for debugging
+ kernel startup, limitations exist (e.g., no stdin, no networking).
+
+ XT2000 is the name of Tensilica's feature-rich emulation platform.
+ This hardware is capable of running a full Linux distribution.
+
+ Xtensa clock calibration
+ CONFIG_XTENSA_CALIBRATE
+ On the XT2000 platform, the CPU clock rate can vary. The frequency
+ can be determined, however, by measuring against the known, fixed
+ frequency of the UART oscillator. The kernel on an XT2000 will
+ always auto-calibrate.
+
+ On the ISS platform, the CPU clock rate is fixed. There is no
+ notion of auto-calibration.
+
+ The ISS and XT2000 platforms are unaffected by this option setting.
+ This option is provided for the benefit of other platforms yet to
+ be defined.
+
Multiquad support for NUMA systems
CONFIG_MULTIQUAD
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