From: James S. <jst...@us...> - 2005-03-06 13:08:29
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Update of /cvsroot/xine/xine-lib/src/video_out/vidix/drivers In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv27353/src/video_out/vidix/drivers Modified Files: Makefile.am cyberblade_regs.h cyberblade_vid.c mach64_vid.c mga_vid.c pm2_vid.c pm3_vid.c radeon_vid.c Added Files: savage_regs.h savage_vid.c Removed Files: nvidia.h Log Message: Sync with vidix cvs --- NEW FILE: savage_regs.h --- /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ #ifndef _SAVAGE_REGS_H #define _SAVAGE_REGS_H /* These are here until xf86PciInfo.h is updated. */ #ifndef PCI_CHIP_S3TWISTER_P #define PCI_CHIP_S3TWISTER_P 0x8d01 #endif #ifndef PCI_CHIP_S3TWISTER_K #define PCI_CHIP_S3TWISTER_K 0x8d02 #endif #ifndef PCI_CHIP_SUPSAV_MX128 #define PCI_CHIP_SUPSAV_MX128 0x8c22 #define PCI_CHIP_SUPSAV_MX64 0x8c24 #define PCI_CHIP_SUPSAV_MX64C 0x8c26 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f #endif #ifndef PCI_CHIP_PROSAVAGE_DDR #define PCI_CHIP_PROSAVAGE_DDR 0x8d03 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 #endif #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) /* Chip tags. These are used to group the adapters into * related families. */ enum S3CHIPTAGS { S3_UNKNOWN = 0, S3_SAVAGE3D, S3_SAVAGE_MX, S3_SAVAGE4, S3_PROSAVAGE, S3_SUPERSAVAGE, S3_SAVAGE2000, S3_LAST }; typedef struct { unsigned int mode, refresh; unsigned char SR08, SR0E, SR0F; unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; unsigned char SR54[8]; unsigned char Clock; unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; unsigned char CR40, CR41, CR42, CR43, CR45; unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; unsigned char CR86, CR88; unsigned char CR90, CR91, CRB0; unsigned int STREAMS[22]; /* yuck, streams regs */ unsigned int MMPR0, MMPR1, MMPR2, MMPR3; } SavageRegRec, *SavageRegPtr; #define BIOS_BSIZE 1024 #define BIOS_BASE 0xc0000 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ #define SAVAGE_NEWMMIO_VGABASE 0x8000 #define BASE_FREQ 14.31818 #define FIFO_CONTROL_REG 0x8200 #define MIU_CONTROL_REG 0x8204 #define STREAMS_TIMEOUT_REG 0x8208 #define MISC_TIMEOUT_REG 0x820c /* Stream Processor 1 */ /* Primary Stream 1 Frame Buffer Address 0 */ #define PRI_STREAM_FBUF_ADDR0 0x81c0 /* Primary Stream 1 Frame Buffer Address 0 */ #define PRI_STREAM_FBUF_ADDR1 0x81c4 /* Primary Stream 1 Stride */ #define PRI_STREAM_STRIDE 0x81c8 /* Primary Stream 1 Frame Buffer Size */ #define PRI_STREAM_BUFFERSIZE 0x8214 /* Secondary stream 1 Color/Chroma Key Control */ #define SEC_STREAM_CKEY_LOW 0x8184 /* Secondary stream 1 Chroma Key Upper Bound */ #define SEC_STREAM_CKEY_UPPER 0x8194 /* Blend Control of Secondary Stream 1 & 2 */ #define BLEND_CONTROL 0x8190 /* Secondary Stream 1 Color conversion/Adjustment 1 */ #define SEC_STREAM_COLOR_CONVERT1 0x8198 /* Secondary Stream 1 Color conversion/Adjustment 2 */ #define SEC_STREAM_COLOR_CONVERT2 0x819c /* Secondary Stream 1 Color conversion/Adjustment 3 */ #define SEC_STREAM_COLOR_CONVERT3 0x81e4 /* Secondary Stream 1 Horizontal Scaling */ #define SEC_STREAM_HSCALING 0x81a0 /* Secondary Stream 1 Frame Buffer Size */ #define SEC_STREAM_BUFFERSIZE 0x81a8 /* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ #define SEC_STREAM_HSCALE_NORMALIZE 0x81ac /* Secondary Stream 1 Horizontal Scaling */ #define SEC_STREAM_VSCALING 0x81e8 /* Secondary Stream 1 Frame Buffer Address 0 */ #define SEC_STREAM_FBUF_ADDR0 0x81d0 /* Secondary Stream 1 Frame Buffer Address 1 */ #define SEC_STREAM_FBUF_ADDR1 0x81d4 /* Secondary Stream 1 Frame Buffer Address 2 */ #define SEC_STREAM_FBUF_ADDR2 0x81ec /* Secondary Stream 1 Stride */ #define SEC_STREAM_STRIDE 0x81d8 /* Secondary Stream 1 Window Start Coordinates */ #define SEC_STREAM_WINDOW_START 0x81f8 /* Secondary Stream 1 Window Size */ #define SEC_STREAM_WINDOW_SZ 0x81fc /* Secondary Streams Tile Offset */ #define SEC_STREAM_TILE_OFF 0x821c /* Secondary Stream 1 Opaque Overlay Control */ #define SEC_STREAM_OPAQUE_OVERLAY 0x81dc /* Stream Processor 2 */ /* Primary Stream 2 Frame Buffer Address 0 */ #define PRI_STREAM2_FBUF_ADDR0 0x81b0 /* Primary Stream 2 Frame Buffer Address 1 */ #define PRI_STREAM2_FBUF_ADDR1 0x81b4 /* Primary Stream 2 Stride */ #define PRI_STREAM2_STRIDE 0x81b8 /* Primary Stream 2 Frame Buffer Size */ #define PRI_STREAM2_BUFFERSIZE 0x8218 /* Secondary Stream 2 Color/Chroma Key Control */ #define SEC_STREAM2_CKEY_LOW 0x8188 /* Secondary Stream 2 Chroma Key Upper Bound */ #define SEC_STREAM2_CKEY_UPPER 0x818c /* Secondary Stream 2 Horizontal Scaling */ #define SEC_STREAM2_HSCALING 0x81a4 /* Secondary Stream 2 Horizontal Scaling */ #define SEC_STREAM2_VSCALING 0x8204 /* Secondary Stream 2 Frame Buffer Size */ #define SEC_STREAM2_BUFFERSIZE 0x81ac /* Secondary Stream 2 Frame Buffer Address 0 */ #define SEC_STREAM2_FBUF_ADDR0 0x81bc /* Secondary Stream 2 Frame Buffer Address 1 */ #define SEC_STREAM2_FBUF_ADDR1 0x81e0 /* Secondary Stream 2 Frame Buffer Address 2 */ #define SEC_STREAM2_FBUF_ADDR2 0x8208 /* Multiple Buffer/LPB and Secondary Stream 2 Stride */ #define SEC_STREAM2_STRIDE_LPB 0x81cc /* Secondary Stream 2 Color conversion/Adjustment 1 */ #define SEC_STREAM2_COLOR_CONVERT1 0x81f0 /* Secondary Stream 2 Color conversion/Adjustment 2 */ #define SEC_STREAM2_COLOR_CONVERT2 0x81f4 /* Secondary Stream 2 Color conversion/Adjustment 3 */ #define SEC_STREAM2_COLOR_CONVERT3 0x8200 /* Secondary Stream 2 Window Start Coordinates */ #define SEC_STREAM2_WINDOW_START 0x820c /* Secondary Stream 2 Window Size */ #define SEC_STREAM2_WINDOW_SZ 0x8210 /* Secondary Stream 2 Opaque Overlay Control */ #define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 /* savage 2000 */ #define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 #define SEC_STREAM_COLOR_CONVERT1_2000 0x819c #define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 #define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 #define SUBSYS_STAT_REG 0x8504 #define SRC_BASE 0xa4d4 #define DEST_BASE 0xa4d8 #define CLIP_L_R 0xa4dc #define CLIP_T_B 0xa4e0 #define DEST_SRC_STR 0xa4e4 #define MONO_PAT_0 0xa4e8 #define MONO_PAT_1 0xa4ec /* Constants for CR69. */ #define CRT_ACTIVE 0x01 #define LCD_ACTIVE 0x02 #define TV_ACTIVE 0x04 #define CRT_ATTACHED 0x10 #define LCD_ATTACHED 0x20 #define TV_ATTACHED 0x40 /* * reads from SUBSYS_STAT */ #define STATUS_WORD0 (INREG(0x48C00)) #define ALT_STATUS_WORD0 (INREG(0x48C60)) #define MAXLOOP 0xffffff #define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) #define MAXFIFO 0x7f00 /* * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. * If not present it will cause lockups on Savage4. * Ask S3, why. */ /*#define VerticalRetraceWait() \ { \ VGAIN8(0x3d0+4); \ VGAOUT8(0x3d0+4, 0x17); \ if (VGAIN8(0x3d0+5) & 0x80) { \ while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ } \ } */ #define VerticalRetraceWait() \ do { \ VGAIN8(0x3d4); \ VGAOUT8(0x3d4, 0x17); \ if (VGAIN8(0x3d5) & 0x80) { \ int i = 0x10000; \ while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ i = 0x10000; \ while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ } \ } while (0) #define I2C_REG 0xa0 #define InI2CREG(a) \ { \ VGAOUT8(0x3d0 + 4, I2C_REG); \ a = VGAIN8(0x3d0 + 5); \ } #define OutI2CREG(a) \ { \ VGAOUT8(0x3d0 + 4, I2C_REG); \ VGAOUT8(0x3d0 + 5, a); \ } #define HZEXP_COMP_1 0x54 #define HZEXP_BORDER 0x58 #define HZEXP_FACTOR_IGA1 0x59 #define VTEXP_COMP_1 0x56 #define VTEXP_BORDER 0x5a #define VTEXP_FACTOR_IGA1 0x5b #define EC1_CENTER_ON 0x10 #define EC1_EXPAND_ON 0x0c #define MODE_24 24 #if (MODE_24 == 32) # define BYTES_PP24 4 #else # define BYTES_PP24 3 #endif #define OVERLAY_DEPTH 16 #define STREAMS_MODE32 0x7 #define STREAMS_MODE24 0x6 #define STREAMS_MODE16 0x5 /* @@@ */ #define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) #define DEPTH_2ND(depth) (depth > 8 ? depth\ : OVERLAY_DEPTH) #define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ STREAMS_MODE24) : STREAMS_MODE16) #define HSCALING_Shift 0 #define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) #define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ << HSCALING_Shift) \ & HSCALING_Mask) #define VSCALING_Shift 0 #define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) #define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ << VSCALING_Shift) \ & VSCALING_Mask) #endif /* _SAVAGE_REGS_H */ --- NEW FILE: savage_vid.c --- /* Driver for S3 Savage Series Copyright (C) 2004 by Reza Jelveh Based on the X11 driver and nvidia vid Thanks to Alex Deucher for Support This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. [...1433 lines suppressed...] break; case FIFO_CONTROL: fprintf(stderr,"FIFO_CONTROL"); break; case PSTREAM_FBSIZE_REG: fprintf(stderr,"PSTREAM_FBSIZE_REG"); break; case SSTREAM_FBSIZE_REG: fprintf(stderr,"SSTREAM_FBSIZE_REG"); break; case SSTREAM_FBADDR2_REG: fprintf(stderr,"SSTREAM_FBADDR2_REG"); break; } fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); } Index: Makefile.am =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/Makefile.am,v retrieving revision 1.14 retrieving revision 1.15 diff -u -r1.14 -r1.15 --- Makefile.am 6 Jan 2005 20:10:52 -0000 1.14 +++ Makefile.am 6 Mar 2005 13:08:11 -0000 1.15 @@ -16,7 +16,8 @@ cyberblade_vid.la \ unichrome_vid.la \ nvidia_vid.la \ - sis_vid.la + sis_vid.la \ + savage_vid.la endif lib_LTLIBRARIES = $(vidix_drivers) @@ -59,8 +60,12 @@ sis_vid_la_SOURCES = sis_vid.c sis_bridge.c sis_vid_la_LDFLAGS = -avoid-version -module -noinst_HEADERS = mach64.h nvidia.h glint_regs.h pm3_regs.h radeon.h \ - cyberblade_regs.h unichrome_regs.h nvidia.h sis_defs.h sis_regs.h +savage_vid_la_SOURCES = savage_vid.c +savage_vid_la_LIBADD = -lm +savage_vid_la_LDFLAGS = -avoid-version -module + +noinst_HEADERS = mach64.h glint_regs.h pm3_regs.h radeon.h savage_regs.h \ + cyberblade_regs.h unichrome_regs.h sis_defs.h sis_regs.h AM_CPPFLAGS = -I$(top_srcdir)/src/video_out/vidix \ -I$(top_srcdir)/src/video_out/libdha \ Index: cyberblade_regs.h =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/cyberblade_regs.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -r1.2 -r1.3 --- cyberblade_regs.h 16 Jan 2003 02:41:42 -0000 1.2 +++ cyberblade_regs.h 6 Mar 2005 13:08:11 -0000 1.3 @@ -133,3 +133,5 @@ #define SROUTB(reg,val) (OUTPORT8(0x3c4,reg), OUTPORT8(0x3c5,val)) /* --- */ + + Index: cyberblade_vid.c =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/cyberblade_vid.c,v retrieving revision 1.5 retrieving revision 1.6 diff -u -r1.5 -r1.6 --- cyberblade_vid.c 12 Dec 2004 06:55:59 -0000 1.5 +++ cyberblade_vid.c 6 Mar 2005 13:08:11 -0000 1.6 @@ -2,6 +2,8 @@ Driver for CyberBlade/i1 - Version 0.1.4 Copyright (C) 2002 by Alastair M. Robinson. + Official homepage: http://www.blackfiveservices.co.uk/EPIAVidix.shtml + Based on Permedia 3 driver by Måns Rullgård Thanks to Gilles Frattini for bugfixes @@ -20,6 +22,14 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Changes: + 18/01/03 + MMIO is no longer used, sidestepping cache issues on EPIA-800 + TV-Out modes are now better supported - this should be the end + of the magenta stripes :) + Brightness/Contrast controls disabled for the time being - they were + seriously degrading picture quality, especially with TV-Out. + To Do: Implement Hue/Saturation controls Support / Test multiple frames @@ -42,10 +52,6 @@ #include "cyberblade_regs.h" -#define CYBERBLADE_MSG "cyberblade_vid:" - -#define VIDIX_STATIC cyberblade_ - pciinfo_t pci_info; char save_colourkey[6]; @@ -58,7 +64,7 @@ #define LOGWRITE(x) #endif -/* Helper functions for reading registers. */ +/* Helper functions for reading registers. */ #if 0 /* unused */ static int CRINW(int reg) @@ -136,7 +142,7 @@ }; -unsigned int VIDIX_NAME(vixGetVersion)(void) +unsigned int vixGetVersion(void) { return(VIDIX_VERSION); } @@ -144,7 +150,12 @@ static unsigned short cyberblade_card_ids[] = { - DEVICE_TRIDENT_CYBERBLADE_I1 + DEVICE_TRIDENT_CYBERBLADE_I7, + DEVICE_TRIDENT_CYBERBLADE_I7D, + DEVICE_TRIDENT_CYBERBLADE_I1, + DEVICE_TRIDENT_CYBERBLADE_I12, + DEVICE_TRIDENT_CYBERBLADE_I13, + DEVICE_TRIDENT_CYBERBLADE_XPAI1 }; @@ -158,7 +169,7 @@ return -1; } -int VIDIX_NAME(vixProbe)(int verbose, int force) +int vixProbe(int verbose, int force) { pciinfo_t lst[MAX_PCI_DEVICES]; unsigned i,num_pci; @@ -166,7 +177,7 @@ err = pci_scan(lst,&num_pci); if(err) { - printf(CYBERBLADE_MSG" Error occured during pci scan: %s\n",strerror(err)); + printf("[cyberblade] Error occurred during pci scan: %s\n",strerror(err)); return err; } else @@ -183,7 +194,7 @@ continue; dname = pci_device_name(VENDOR_TRIDENT, lst[i].device); dname = dname ? dname : "Unknown chip"; - printf(CYBERBLADE_MSG" Found chip: %s\n", dname); + printf("[cyberblade] Found chip: %s\n", dname); cyberblade_cap.device_id = lst[i].device; err = 0; memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); @@ -192,14 +203,14 @@ } } - if(err && verbose) printf(CYBERBLADE_MSG" Can't find chip\n"); + if(err && verbose) printf("[cyberblade] Can't find chip\n"); return err; } -int VIDIX_NAME(vixInit)(const char *args) +int vixInit(const char *args) { - cyberblade_mem = map_phys_mem(pci_info.base0, 0x800000); + cyberblade_mem = map_phys_mem(pci_info.base0, 0x800000); enable_app_io(); save_colourkey[0]=SRINB(0x50); save_colourkey[1]=SRINB(0x51); @@ -213,7 +224,7 @@ return 0; } -void VIDIX_NAME(vixDestroy)(void) +void vixDestroy(void) { int protect; #ifdef DEBUG_LOGFILE @@ -231,10 +242,11 @@ SROUTB(0x56,save_colourkey[5]); SROUTB(0x11, protect); disable_app_io(); + unmap_phys_mem(cyberblade_mem, 0x800000); } -int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +int vixGetCapability(vidix_capability_t *to) { memcpy(to, &cyberblade_cap, sizeof(vidix_capability_t)); return 0; @@ -247,6 +259,7 @@ { case IMGFMT_YUY2: case IMGFMT_YV12: + case IMGFMT_I420: case IMGFMT_YVU9: case IMGFMT_BGR16: return 1; @@ -277,17 +290,17 @@ static vidix_grkey_t cyberblade_grkey; -int VIDIX_NAME(vixGetGrKeys)(vidix_grkey_t *grkey) +int vixGetGrKeys(vidix_grkey_t *grkey) { memcpy(grkey, &cyberblade_grkey, sizeof(vidix_grkey_t)); return(0); } -int VIDIX_NAME(vixSetGrKeys)(const vidix_grkey_t *grkey) +int vixSetGrKeys(const vidix_grkey_t *grkey) { int pixfmt=CRINB(0x38); int protect; - memcpy(&cyberblade_grkey, grkey, sizeof(vidix_grkey_t)); + memcpy(&cyberblade_grkey, grkey, sizeof(vidix_grkey_t)); protect=SRINB(0x11); SROUTB(0x11, 0x92); @@ -324,13 +337,13 @@ 300, 100, 0, 0, 0, 0, 0, 0 }; -int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq) +int vixPlaybackGetEq( vidix_video_eq_t * eq) { memcpy(eq,&equal,sizeof(vidix_video_eq_t)); return 0; } -int VIDIX_NAME(vixPlaybackSetEq)( const vidix_video_eq_t * eq) +int vixPlaybackSetEq( const vidix_video_eq_t * eq) { int br,sat,cr,protect; if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; @@ -370,7 +383,7 @@ static int YOffs,UOffs,VOffs; -int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info) +int vixConfigPlayback(vidix_playback_t *info) { int src_w, drw_w; int src_h, drw_h; @@ -401,6 +414,7 @@ layout=0x0; /* packed */ break; case IMGFMT_YV12: + case IMGFMT_I420: y_pitch = (src_w+15) & ~15; uv_pitch = ((src_w/2)+7) & ~7; YOffs=info->offset.y = 0; @@ -452,7 +466,7 @@ SROUTB(0x21, 0x34); /* Signature control */ SROUTB(0x37, 0x30); /* Video key mode */ - vixSetGrKeys(&cyberblade_grkey); + vixSetGrKeys(&cyberblade_grkey); /* compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); */ { @@ -460,18 +474,18 @@ int HWinStart,VWinStart; int tx1,ty1,tx2,ty2; - HTotal=CRINB(0x00); - HSync=CRINB(0x04); - VTotal=CRINB(0x06); - VSync=CRINB(0x10); - Overflow=CRINB(0x07); - HTotal <<=3; - HSync <<=3; - VTotal |= (Overflow & 1) <<8; - VTotal |= (Overflow & 0x20) <<4; - VTotal +=4; - VSync |= (Overflow & 4) <<6; - VSync |= (Overflow & 0x80) <<2; + HTotal=CRINB(0x00); + HSync=CRINB(0x04); + VTotal=CRINB(0x06); + VSync=CRINB(0x10); + Overflow=CRINB(0x07); + HTotal <<=3; + HSync <<=3; + VTotal |= (Overflow & 1) <<8; + VTotal |= (Overflow & 0x20) <<4; + VTotal +=4; + VSync |= (Overflow & 4) <<6; + VSync |= (Overflow & 0x80) <<2; if(CRINB(0xd1)&0x80) { @@ -499,18 +513,15 @@ HWinStart=(TVHTotal-HDisp)&15; HWinStart|=(HTotal-HDisp)&15; HWinStart+=(TVHTotal-TVHSyncStart)-49; - - VWinStart=(TVVTotal-VDisp)/2-1; - VWinStart-=(1-((TVVTotal-VDisp)&1))+4; } else { LOGWRITE("[cyberblade] Using Standard CRTC\n"); HWinStart=(HTotal-HSync)+15; - VWinStart=(VTotal-VSync)-8; } + VWinStart=(VTotal-VSync)-8; - printf(CYBERBLADE_MSG" HTotal: 0x%x, HSStart: 0x%x\n",HTotal,HSync); + printf("[cyberblade] HTotal: 0x%x, HSStart: 0x%x\n",HTotal,HSync); printf(" VTotal: 0x%x, VStart: 0x%x\n",VTotal,VSync); tx1=HWinStart+info->dest.x; ty1=VWinStart+info->dest.y; @@ -596,7 +607,7 @@ } -int VIDIX_NAME(vixPlaybackOn)(void) +int vixPlaybackOn(void) { LOGWRITE("Enable overlay\n"); CROUTB(0x8E, 0xd4); /* VDE Flags*/ @@ -605,7 +616,7 @@ } -int VIDIX_NAME(vixPlaybackOff)(void) +int vixPlaybackOff(void) { LOGWRITE("Disable overlay\n"); CROUTB(0x8E, 0xc4); /* VDE Flags*/ @@ -614,7 +625,7 @@ } -int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame) +int vixPlaybackFrameSelect(unsigned int frame) { int protect; LOGWRITE("Frame select\n"); @@ -635,3 +646,4 @@ } + Index: mach64_vid.c =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/mach64_vid.c,v retrieving revision 1.9 retrieving revision 1.10 diff -u -r1.9 -r1.10 --- mach64_vid.c 12 Dec 2004 06:55:59 -0000 1.9 +++ mach64_vid.c 6 Mar 2005 13:08:11 -0000 1.10 @@ -32,8 +32,6 @@ #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ -#define MACH64_MSG "mach64_vid:" - #define VIDIX_STATIC mach64_ #ifdef MACH64_ENABLE_BM @@ -333,7 +331,7 @@ int yres= mach64_get_yres(); if(!supports_lcd_v_stretch){ - if(__verbose>0) printf(MACH64_MSG" vertical stretching not supported\n"); + if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); return 1<<16; } @@ -356,7 +354,7 @@ OUTREG(LCD_INDEX, lcd_index); - if(__verbose>0) printf(MACH64_MSG" vertical stretching factor= %d\n", ret); + if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); return ret; } @@ -379,20 +377,20 @@ static void mach64_vid_dump_regs( void ) { size_t i; - printf(MACH64_MSG" *** Begin of DRIVER variables dump ***\n"); - printf(MACH64_MSG" mach64_mmio_base=%p\n",mach64_mmio_base); - printf(MACH64_MSG" mach64_mem_base=%p\n",mach64_mem_base); - printf(MACH64_MSG" mach64_overlay_off=%08X\n",mach64_overlay_offset); - printf(MACH64_MSG" mach64_ram_size=%08X\n",mach64_ram_size); - printf(MACH64_MSG" video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); - printf(MACH64_MSG" *** Begin of OV0 registers dump ***\n"); + printf("[mach64] *** Begin of DRIVER variables dump ***\n"); + printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); + printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); + printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); + printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); + printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); + printf("[mach64] *** Begin of OV0 registers dump ***\n"); for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) { mach64_wait_for_idle(); mach64_fifo_wait(2); - printf(MACH64_MSG" %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); + printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); } - printf(MACH64_MSG" *** End of OV0 registers dump ***\n"); + printf("[mach64] *** End of OV0 registers dump ***\n"); } @@ -470,7 +468,7 @@ err = pci_scan(lst,&num_pci); if(err) { - printf(MACH64_MSG" Error occured during pci scan: %s\n",strerror(err)); + printf("[mach64] Error occured during pci scan: %s\n",strerror(err)); return err; } else @@ -486,12 +484,12 @@ if(idx == -1 && force == PROBE_NORMAL) continue; dname = pci_device_name(VENDOR_ATI,lst[i].device); dname = dname ? dname : "Unknown chip"; - printf(MACH64_MSG" Found chip: %s\n",dname); + printf("[mach64] Found chip: %s\n",dname); if(force > PROBE_NORMAL) { - printf(MACH64_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); if(idx == -1) - printf(MACH64_MSG" Assuming it as Mach64\n"); + printf("[mach64] Assuming it as Mach64\n"); } if(idx != -1) is_agp = ati_card_ids[idx].is_agp; mach64_cap.device_id = lst[i].device; @@ -502,7 +500,7 @@ } } } - if(err && verbose) printf(MACH64_MSG" Can't find chip\n"); + if(err && verbose) printf("[mach64] Can't find chip\n"); return err; } @@ -563,11 +561,11 @@ 2,CRTC_INT_CNTL,CRTC_BUSMASTER_EOL_INT) == 0) { can_use_irq=1; - if(__verbose) printf(MACH64_MSG" Will use %u irq line\n",pci_info.irq); + if(__verbose) printf("[mach64] Will use %u irq line\n",pci_info.irq); } else - if(__verbose) printf(MACH64_MSG" Can't initialize irq handling: %s\n" - MACH64_MSG"irq_param: line=%u pin=%u gnt=%u lat=%u\n" + if(__verbose) printf("[mach64] Can't initialize irq handling: %s\n" + "[mach64]irq_param: line=%u pin=%u gnt=%u lat=%u\n" ,strerror(errno) ,pci_info.irq,pci_info.ipin,pci_info.gnt,pci_info.lat); } @@ -581,15 +579,15 @@ #endif if(!probed) { - printf(MACH64_MSG" Driver was not probed but is being initializing\n"); + printf("[mach64] Driver was not probed but is being initializing\n"); return EINTR; } - if(__verbose>0) printf(MACH64_MSG" version %d args='%s'\n", VIDIX_VERSION,args); + if(__verbose>0) printf("[mach64] version %d args='%s'\n", VIDIX_VERSION,args); if(args) if(strncmp(args,"irq=",4) == 0) { forced_irq=atoi(&args[4]); - if(__verbose>0) printf(MACH64_MSG" forcing IRQ to %u\n",forced_irq); + if(__verbose>0) printf("[mach64] forcing IRQ to %u\n",forced_irq); } if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; @@ -601,9 +599,9 @@ mach64_ram_size *= 0x400; /* KB -> bytes */ if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; memset(&besr,0,sizeof(bes_registers_t)); - printf(MACH64_MSG" Video memory = %uMb\n",mach64_ram_size/0x100000); + printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); - if(!err) printf(MACH64_MSG" Set write-combining type of video memory\n"); + if(!err) printf("[mach64] Set write-combining type of video memory\n"); save_regs(); /* check if planar formats are supported */ @@ -621,7 +619,7 @@ if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; } - printf(MACH64_MSG" Planar YUV formats are %s supported\n",supports_planar?"":"not"); + printf("[mach64] Planar YUV formats are %s supported\n",supports_planar?"":"not"); supports_colour_adj=0; OUTREG(SCALER_COLOUR_CNTL,-1); if(INREG(SCALER_COLOUR_CNTL)) supports_colour_adj=1; @@ -629,12 +627,12 @@ OUTREG(IDCT_CONTROL,-1); if(INREG(IDCT_CONTROL)) supports_idct=1; OUTREG(IDCT_CONTROL,0); - printf(MACH64_MSG" IDCT is %s supported\n",supports_idct?"":"not"); + printf("[mach64] IDCT is %s supported\n",supports_idct?"":"not"); supports_subpic=0; OUTREG(SUBPIC_CNTL,-1); if(INREG(SUBPIC_CNTL)) supports_subpic=1; OUTREG(SUBPIC_CNTL,0); - printf(MACH64_MSG" subpictures are %s supported\n",supports_subpic?"":"not"); + printf("[mach64] subpictures are %s supported\n",supports_subpic?"":"not"); if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L @@ -655,7 +653,7 @@ if((dma_phys_addrs = malloc(mach64_ram_size*sizeof(unsigned long)/4096)) == 0) { out_mem: - printf(MACH64_MSG" Can't allocate temporary buffer for DMA\n"); + printf("[mach64] Can't allocate temporary buffer for DMA\n"); mach64_cap.flags &= ~FLAG_DMA & ~FLAG_EQ_DMA; return 0; } @@ -678,7 +676,7 @@ #endif } else - if(__verbose) printf(MACH64_MSG" Can't initialize busmastering: %s\n",strerror(errno)); + if(__verbose) printf("[mach64] Can't initialize busmastering: %s\n",strerror(errno)); #endif return 0; } @@ -946,7 +944,7 @@ } } #endif - if(__verbose>0) printf(MACH64_MSG" ecp: %d\n", ecp); + if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); v_inc = src_h * mach64_get_vert_stretch(); if(mach64_is_interlace()) v_inc<<=1; @@ -1076,7 +1074,7 @@ if(!is_supported_fourcc(info->fourcc)) return ENOSYS; if(info->src.h > 720 || info->src.w > 720) { - printf(MACH64_MSG" Can't apply width or height > 720\n"); + printf("[mach64] Can't apply width or height > 720\n"); return EINVAL; } if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; @@ -1121,8 +1119,8 @@ err = INREG(SCALER_BUF_PITCH) == besr.vid_buf_pitch ? 0 : EINTR; if(err) { - printf(MACH64_MSG" *** Internal fatal error ***: Detected pitch corruption\n" - MACH64_MSG" Try decrease number of buffers\n"); + printf("[mach64] *** Internal fatal error ***: Detected pitch corruption\n" + "[mach64] Try decrease number of buffers\n"); } return err; } @@ -1148,7 +1146,7 @@ off[i] = mach64_buffer_base[frame][i]; off[i+3]= mach64_buffer_base[last_frame][i]; } - if(__verbose > VERBOSE_LEVEL) printf(MACH64_MSG" flip_page = %u\n",frame); + if(__verbose > VERBOSE_LEVEL) printf("mach64_vid: flip_page = %u\n",frame); #if 0 // delay routine so the individual frames can be ssen better { Index: mga_vid.c =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/mga_vid.c,v retrieving revision 1.14 retrieving revision 1.15 diff -u -r1.14 -r1.15 --- mga_vid.c 10 Jan 2005 20:05:49 -0000 1.14 +++ mga_vid.c 6 Mar 2005 13:08:11 -0000 1.15 @@ -76,10 +76,10 @@ #ifdef CRTC2 #define VIDIX_STATIC mga_crtc2_ -#define MGA_MSG "mga_crtc2_vid:" +#define MGA_MSG "[mga_crtc2]" #else #define VIDIX_STATIC mga_ -#define MGA_MSG "mga_vid:" +#define MGA_MSG "[mga]" #endif /* from radeon_vid */ Index: pm2_vid.c =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/pm2_vid.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -r1.1 -r1.2 --- pm2_vid.c 14 Jan 2003 01:57:00 -0000 1.1 +++ pm2_vid.c 6 Mar 2005 13:08:12 -0000 1.2 @@ -34,8 +34,6 @@ #include "glint_regs.h" -#define PM2_MSG "pm2_vid:" - #define VIDIX_STATIC pm2_ /* MBytes of video memory to use */ @@ -109,7 +107,7 @@ err = pci_scan(lst,&num_pci); if(err) { - printf(PM2_MSG" Error occured during pci scan: %s\n",strerror(err)); + printf("[pm2] Error occured during pci scan: %s\n",strerror(err)); return err; } else @@ -124,21 +122,21 @@ continue; dname = pci_device_name(lst[i].vendor, lst[i].device); dname = dname ? dname : "Unknown chip"; - printf(PM2_MSG" Found chip: %s\n", dname); + printf("[pm2] Found chip: %s\n", dname); pm2_cap.device_id = lst[i].device; err = 0; memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); break; } } - if(err && verbose) printf(PM2_MSG" Can't find chip.\n"); + if(err && verbose) printf("[pm2] Can't find chip.\n"); return err; } #define PRINT_REG(reg) \ { \ long _foo = READ_REG(reg); \ - printf(PM2_MSG" " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ + printf("[pm2] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ } int VIDIX_NAME(vixInit)(const char *args) Index: pm3_vid.c =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/pm3_vid.c,v retrieving revision 1.6 retrieving revision 1.7 diff -u -r1.6 -r1.7 --- pm3_vid.c 13 Jan 2004 21:56:15 -0000 1.6 +++ pm3_vid.c 6 Mar 2005 13:08:12 -0000 1.7 @@ -34,8 +34,6 @@ #include "pm3_regs.h" -#define PM3_MSG "pm3_vid:" - #define VIDIX_STATIC pm3_ /* MBytes of video memory to use */ @@ -109,7 +107,7 @@ err = pci_scan(lst,&num_pci); if(err) { - printf(PM3_MSG" Error occured during pci scan: %s\n",strerror(err)); + printf("[pm3] Error occured during pci scan: %s\n",strerror(err)); return err; } else @@ -126,7 +124,7 @@ continue; dname = pci_device_name(VENDOR_3DLABS, lst[i].device); dname = dname ? dname : "Unknown chip"; - printf(PM3_MSG" Found chip: %s with IRQ %i\n", + printf("[pm3] Found chip: %s with IRQ %i\n", dname, lst[i].irq); pm3_cap.device_id = lst[i].device; err = 0; @@ -135,14 +133,14 @@ } } } - if(err && verbose) printf(PM3_MSG" Can't find chip\n"); + if(err && verbose) printf("[pm3] Can't find chip\n"); return err; } #define PRINT_REG(reg) \ { \ long _foo = READ_REG(reg); \ - printf(PM3_MSG" " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ + printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ } int VIDIX_NAME(vixInit)(const char *args) @@ -173,7 +171,7 @@ pm3_mem = map_phys_mem(pci_info.base1, 0x2000000); if(bm_open() == 0){ - fprintf(stderr, PM3_MSG" DMA available.\n"); + fprintf(stderr, "[pm3] DMA available.\n"); pm3_cap.flags |= FLAG_DMA | FLAG_SYNC_DMA; page_size = sysconf(_SC_PAGESIZE); hwirq_install(pci_info.bus, pci_info.card, pci_info.func, Index: radeon_vid.c =================================================================== RCS file: /cvsroot/xine/xine-lib/src/video_out/vidix/drivers/radeon_vid.c,v retrieving revision 1.16 retrieving revision 1.17 diff -u -r1.16 -r1.17 --- radeon_vid.c 6 Jan 2005 20:10:53 -0000 1.16 +++ radeon_vid.c 6 Mar 2005 13:08:12 -0000 1.17 @@ -22,10 +22,10 @@ #include "radeon.h" #ifdef RAGE128 -#define RADEON_MSG "rage128_vid:" +#define RADEON_MSG "[rage128]" #define X_ADJUST 0 #else -#define RADEON_MSG "radeon_vid:" +#define RADEON_MSG "[radeon]" #define X_ADJUST (((besr.chip_flags&R_OVL_SHIFT)==R_OVL_SHIFT)?8:0) #ifndef RADEON #define RADEON @@ -266,8 +266,12 @@ #define R_280 0x00000006 #define R_300 0x00000007 #define R_350 0x00000008 +#define R_370 0x00000010 +#define R_380 0x00000020 +#define R_420 0x00000040 #define R_OVL_SHIFT 0x00000100 #define R_INTEGRATED 0x00000200 +#define R_PCIE 0x00000400 typedef struct ati_card_ids_s { @@ -386,7 +390,6 @@ { DEVICE_ATI_R300_AG_FIREGL, R_300 }, { DEVICE_ATI_RADEON_R300_ND, R_300 }, { DEVICE_ATI_RADEON_R300_NE, R_300 }, - { DEVICE_ATI_RV350_NF_RADEON, R_300 }, { DEVICE_ATI_RADEON_R300_NG, R_300 }, { DEVICE_ATI_R300_AD_RADEON, R_300 }, { DEVICE_ATI_R300_AE_RADEON, R_300 }, @@ -396,22 +399,44 @@ { DEVICE_ATI_R350_AH_RADEON, R_350 }, { DEVICE_ATI_R350_AI_RADEON, R_350 }, { DEVICE_ATI_R350_AJ_RADEON, R_350 }, - { DEVICE_ATI_R350_AK_FIRE, R_350 }, + { DEVICE_ATI_R350_AK_FIRE, R_350 }, { DEVICE_ATI_RADEON_R350_RADEON2, R_350 }, { DEVICE_ATI_RADEON_R350_RADEON3, R_350 }, { DEVICE_ATI_RV350_NJ_RADEON, R_350 }, - { DEVICE_ATI_R350_NK_FIRE, R_350 }, + { DEVICE_ATI_R350_NK_FIRE, R_350 }, { DEVICE_ATI_RV350_AP_RADEON, R_350 }, { DEVICE_ATI_RV350_AQ_RADEON, R_350 }, { DEVICE_ATI_RV350_AR_RADEON, R_350 }, + { DEVICE_ATI_RV350_AS_RADEON, R_350 }, { DEVICE_ATI_RV350_AT_FIRE, R_350 }, + { DEVICE_ATI_RV350_AU_FIRE, R_350 }, { DEVICE_ATI_RV350_AV_FIRE, R_350 }, - { DEVICE_ATI_RV350_MOBILITY_RADEON,R_350 }, + { DEVICE_ATI_RV350_AW_FIRE, R_350 }, + { DEVICE_ATI_RV350_MOBILITY_RADEON, R_350 }, + { DEVICE_ATI_RV350_NF_RADEON, R_300 }, + { DEVICE_ATI_RV350_NJ_RADEON, R_300 }, { DEVICE_ATI_M10_NQ_RADEON, R_350 }, - { DEVICE_ATI_RV350_MOBILITY_RADEON2,R_350 }, + { DEVICE_ATI_RV350_MOBILITY_RADEON2, R_350 }, { DEVICE_ATI_M10_NS_RADEON, R_350 }, { DEVICE_ATI_M10_NT_FIREGL, R_350 }, - { DEVICE_ATI_M11_NV_FIREGL, R_350 } + { DEVICE_ATI_M11_NV_FIREGL, R_350 }, + { DEVICE_ATI_RV370_5B60_RADEON, R_370|R_PCIE }, + { DEVICE_ATI_RV370_5B62_RADEON, R_370|R_PCIE }, + { DEVICE_ATI_RV370_5B64_FIREGL, R_370|R_PCIE }, + { DEVICE_ATI_RV370_5B65_FIREGL, R_370|R_PCIE }, + { DEVICE_ATI_RV380_0X3E50_RADEON, R_380|R_PCIE }, + { DEVICE_ATI_RV380_0X3E54_FIREGL, R_380|R_PCIE }, + { DEVICE_ATI_RV380_RADEON_X600, R_380|R_PCIE }, + { DEVICE_ATI_R420_JH_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JI_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JJ_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JK_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JL_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JM_FIREGL, R_420|R_PCIE }, + { DEVICE_ATI_M18_JN_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JP_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JM_FIREGL, R_420|R_PCIE }, + { DEVICE_ATI_R423_5F57_RADEON, R_420|R_PCIE } #endif }; --- nvidia.h DELETED --- |