Re: [Xc3sprog-users] bscan 59a6 bug

[joosteto <joo...@gm...>]

Ah, forgot one bit!
The code I sent before forgot to write the TDI after a reset.

So this should be better (not tried to build, have no access to an ISE at
the moment)

//add one line to the declarations:
   reg         RAM_WE = 0;
//and then, in the last process
   always @(posedge DRCK1 or posedge rst)
     if (rst)
       begin
          CS_GO <= 0;
          CS_STOP_PREP <= 0;
          RAM_WADDR <= 0;
          RAM_RADDR <=0;
          RAM_WE <= 0;
//add one line:
          reset_header <= 1;
       end
     else
       begin
          RAM_RADDR <= RAM_RADDR + 1;
          RAM_WE <= !CSB;
          if(RAM_WE)

            RAM_WADDR <= RAM_WADDR + 1;
//change:
          reset_header <=0;
          //I assume in Verilog the next if statment also tests
          //the value of reset_header at time of clock, so it will test true
          //the first clock after a reset:
          if(reset_header)
            header <={47'h000000000000, TDI};  //is this how verilog sets
all bits to 0 + TDI?
          else
            header <= {header[46:0], TDI};
//end change
          CS_GO <= CS_GO_PREP;
          if (CS_GO && (len == 0))
            CS_STOP_PREP <= 1;
       end // else: !if(CAPTURE || RESET || UPDATE || !SEL1)



On 19 June 2013 12:19, joosteto <joo...@gm...> wrote:

> > Two problems:
> > - "I had to change a lot more to make it work" doesn't sound good. Please
> >   explain the problems or explain why they don't generally apply
>
> Well, all the other changes were to make the original bscan_s3_spi_isf.vhd
> work for my Xilinx ISI 14.5 /  xc3s500e:
>  * Orignial had an emtpy "entity" header; my ISE didn't like that, so I
> added a port definition (with ports list), and removed those signals from
> the signal list.
>  * It apears the original was for a Spartan-3A, as the "BSCAN_SPARTAN3A"
> component wasn't accepted when building for my xc3s500e, so changed it to
> "BSCAN_SPARTAN3"; this change then also meant I had to remove TCK, TMS from
> the port list.
>  * the SPI_ACCESS component wasn't known; simply removing it altogether
> worked.
>
> So non of those changes had any relation to the bug we're discussing here.
>
> > - I have to rewrite your patch for Verilog, so can you explain what
> "header <= (0=> TDI, others=>'0');" does?
>
> It does the same as it did in the original; the Verilog equivalent must be
>  header <= {header[46:0], TDI};
>
> I suppose the full section of the verilog code will be:
> //add one line to the declarations:
>    reg         RAM_WE = 0;
> //and then, in the last process
>    always @(posedge DRCK1 or posedge rst)
>      if (rst)
>        begin
>           CS_GO <= 0;
>           CS_STOP_PREP <= 0;
>           RAM_WADDR <= 0;
>           RAM_RADDR <=0;
>           RAM_WE <= 0;
> //add one line:
>           reset_header <= 1;
>        end
>      else
>        begin
>           RAM_RADDR <= RAM_RADDR + 1;
>           RAM_WE <= !CSB;
>           if(RAM_WE)
>
>             RAM_WADDR <= RAM_WADDR + 1;
> //change:
>           reset_header <=0;
>           //I assume in Verilog the next if statment also tests
>           //the value of reset_header at time of clock, so it will test
> true
>           //the first clock after a reset:
>           if(reset_header)
>             header <=48'h000000000000;  //is this how verilog sets all
> bits to 0?
>           else
>             header <= {header[46:0], TDI};
> //end change
>           CS_GO <= CS_GO_PREP;
>           if (CS_GO && (len == 0))
>             CS_STOP_PREP <= 1;
>        end // else: !if(CAPTURE || RESET || UPDATE || !SEL1)
>
>
>
> On 19 June 2013 11:49, Uwe Bonnes <bo...@el...
> > wrote:
>
>> >>>>> "joosteto" == joosteto  <joo...@gm...> writes:
>>
>> ...
>>     joosteto> I actually proposed two fixes (maybe I sent too many emails
>> to
>>     joosteto> the list...), the second was to fix the scan*.vhdl FPGA
>> code,
>>     joosteto> and reset the header data whenever it sets have_header to 0.
>>
>> Probably other thing draw my attention.
>>
>>     joosteto> The advantage of that fix is that old scan*.bit files will
>>     joosteto> still work (just not with the 59a6 data), and no fix to the
>>     joosteto> .cpp files need to be applied.
>>
>>     joosteto> Here's the relavant part of my email from june the 6th again
>>     joosteto> (reworded):
>>
>>     joosteto> Another (more backward compatible) fix would be making the
>>     joosteto> bscan code reset the read header each time it sets
>>     joosteto> "have_header<='0'".
>>
>>     joosteto> I modified my bscan_s3_spi_isf.vhdl as described below (with
>>     joosteto> the old 59a659a6 magic); and now I can upload files with
>> 59a6
>>     joosteto> in them (and any other data I tried).
>>
>>     joosteto> Here's my bscan_s3_spi_isf.vhdl:
>>     joosteto>
>> http://tech.komputilo.org/images/1/12/Bscan_s3_spi_isf-reset.vhdl
>>
>>     joosteto> The relevant part (I had to change a lot more to make it
>> work
>>     joosteto> for my xcs3s500e FPGA) of the patch is:
>>
>> Two problems:
>> - "I had to change a lot more to make it work" doesn't sound good. Please
>> explain the problems or explain why they don't generally apply
>> - I have to rewrite your patch for Verilog, so can you explain what
>> "header <= (0=> TDI, others=>'0');" does?
>>
>> Bye
>>
>> --
>> Uwe Bonnes                bo...@el...
>>
>> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
>> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>>
>
>