Re: [Xc3sprog-users] Vertex 6

[Matthew L. <li...@bu...>]

>>>>>> "Matthew" == Matthew Lear <li...@bu...> writes:
>
>     >> You first shot should be to add the FAMILY_XCV6xxxx definitions in
>     >> progalgxc3s.h and then add FAMILY_XCV6xxxx to the Xc5V clause in
>     >> ProgAlgXC3S::ProgAlgXC3S. Perhaps than everything works already...
>
>     Matthew> Ok, thanks. I just wanted to check one thing. Looking at the
>     Matthew> current Virtex 5 settings in ProgAlgXC3S::ProgAlgXC3S,
>     Matthew> array_transfer_len is specified to be 32 but the Xilinx
> Virtex
>     Matthew> 5 FPGA Configuration User Guide (UG191) states to load 64
> bits
>     Matthew> of bitstream data followed by RTI (1 x TCK cycle) after
>     Matthew> ISC_PROGRAM. Does this mean that the value for
>     Matthew> array_transfer_len is incorrect or have I missed something?
> Compare the XC5V and XC6V 1532 algorithm encoded in files like
>
> Xilinx/13.4/ISE_DS/ISE/virtex5/data/xc5vlx20t_1532.bsd
>
> and
>
> Xilinx/13.4/ISE_DS/ISE/virtex6/data/xc6vcx75t_1532.bsd
>
> found where ISE is installed. I think there is no big difference, if there
> is a difference at all. If there is no difference, the XC5V settings
> should
> work or if they don't work with XC6V there is something fishy and that
> should be fixed. If there are differences,thy should be encoded...
>
> Hope this helps.

Thanks Uwe. Yes.

"       (ISC_PROGRAM    32:?    wait TCK 1 )," &

This section is the same for both devices -> so same as Virtex5. I
personally have no Xilinx eval board to test easily with an ftdi part, but
our custom hw is due back in a week or so, so not too long to wait. I hope
to have some good news for you then :-)
Cheers,
--  Matt