Re: [Xc3sprog-users] Vertex 6

[Matthew L. <li...@bu...>]

> You first shot should be to add the FAMILY_XCV6xxxx definitions in
> progalgxc3s.h and then add FAMILY_XCV6xxxx to the Xc5V clause in
> ProgAlgXC3S::ProgAlgXC3S. Perhaps than everything works already...

Ok, thanks. I just wanted to check one thing. Looking at the current
Virtex 5 settings in ProgAlgXC3S::ProgAlgXC3S, array_transfer_len is
specified to be 32 but the Xilinx Virtex 5 FPGA Configuration User Guide
(UG191) states to load 64 bits of bitstream data followed by RTI (1 x TCK
cycle) after ISC_PROGRAM. Does this mean that the value for
array_transfer_len is incorrect or have I missed something?
Cheers,
--  Matt