From: Uwe B. <bo...@el...> - 2011-08-28 18:02:50
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>>>>> "Tomek" == Tomek CEDRO <tom...@gm...> writes: ... Tomek> The problem I have is that bitfile does not upload into SPI Tomek> correctly because there are errors during the flash. I can upload Tomek> bitfile directly into FPGA with no problem :-) This might be Tomek> caused by too fast speed of Xilinx cable that cannot be changed, Tomek> I will try to use FT2232 cable instead and let you know the Tomek> results :-) Please test with the FTx232 cable. If it works, this will take the preasure off and we know that the problem is with xc3sprog/xilinx cable. To slow down the JTAG frequency, use the -J xxx argument- If the problem persists, you know that the problem is with your chain. Bye -- Uwe Bonnes bo...@el... Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- |