From: Uwe B. <bo...@el...> - 2010-07-10 14:51:02
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>>>>> "Joris" == Joris van Rantwijk <jo...@sr...> writes: Joris> On Friday, July 09, 2010 11:15:13 Uwe Bonnes wrote: >> What is the program time now? Joris> About 480 seconds to program 24 Mbit. Versus 140 in Impact. Bad... Joris> In the Linux kernel that I used, the option for high resolution Joris> timing was turned off. Today I figured out that high resolution Joris> timing greatly improves the accuracy of usleep. I will enable Joris> this setting and test again next week. At some point in time I will switch to libusb-1.0 and use asynchronous read. This could bring downprogramming time to. >> Btw: Any chance to look at the TDO driving gate on the S3 kit? Joris> I did not precisely understand your remarks (I'm not an Joris> electronics engineer). But let's try. On the S3 starter kit Joris> schematics, the type of IC2A is not specified. On the actual Joris> board, I can see an IC2 which is a tiny surface mounted thingy, Joris> marked something like "WOC". Any manufacturer sign visible? The smd marking sites don't bring anything sensible with WOC. But I think it is a "strong" device. Joris> The Pender GR-XC3S1500 also fails with the parallel cable. Its Joris> schematic shows that TDO is driven directly from the FPGA's TDO Joris> pin without any components in between. But the FPGA TDO output should also be "strong", so it will win against the "weak" HC125 on the DLC5. On my clone is a "strong" LVC125, so my results are different. I will drop this unreliable test soon. Joris> Just to be sure, let me say again that the issue is only with the Joris> check for "missing power" at initialization time (which then Joris> aborts the program). If that check is skipped, programming with Joris> the parallel cable works absolutely fine for me. Another reason to drop the test. Cheers -- Uwe Bonnes bo...@el... Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- |