[Xc3sprog-users] Xilinx DLC10 cable support from urjtag/src/tap/cable/xpc.c

[Uwe B. <bo...@el...>]

Hello,

I have adapted Kolja Waschk' reversed engineered urjtag/src/tap/cable/xpc.c
for xc3sprog. Tested with a DLC10 by loading the bscan_spi pattern to the
XC3SD1800 from a ADSP Starter board. After substantially increasing the
buffer size, as opposed to Kolja's observation with a DLC9, speed now is only
about half as slow (6 seconds) as impact(3 seconds), while it crawled before
with the original buffer size.

Cheers
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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