[Wisp-cvs] wisp/users/dig i80386.tran,NONE,1.1 Makefile.am,1.14,1.15 hello.tran,1.2,1.3 ia32.tran,1.
Status: Alpha
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Update of /cvsroot/wisp/wisp/users/dig In directory sc8-pr-cvs1:/tmp/cvs-serv22992 Modified Files: Makefile.am hello.tran ia32.tran mswhello.tran tran-builtins tran.py Added Files: i80386.tran Log Message: extracted i80386.tran from ia32.tran --- NEW FILE: i80386.tran --- \\\\ i80386.tran - Intel's 80386 instructions \ \ Copyleft © 2003 by Andres Soolo (di...@us...) \ This file is licensed under the GNU GPL v2. If you \ don't know what that means, please do read the GPL. \ \\\\ @(#) $Id: i80386.tran,v 1.1 2003/05/17 05:37:51 digg Exp $ include i8086 \ registers :regs reg32 %eax %ecx %edx %ebx %esp %ebp %esi %edi ; Index: Makefile.am =================================================================== RCS file: /cvsroot/wisp/wisp/users/dig/Makefile.am,v retrieving revision 1.14 retrieving revision 1.15 diff -u -d -r1.14 -r1.15 --- Makefile.am 17 May 2003 04:45:02 -0000 1.14 +++ Makefile.am 17 May 2003 05:37:51 -0000 1.15 @@ -8,7 +8,7 @@ EXTRA_DIST = .cvsignore .pycheckrc struburn.wisp bits.py linkie.py \ coff.py elf.py pe.py \ - i8086.tran ia32.tran hello.tran winapi.tran mswhello.tran \ + i8086.tran i80386.tran ia32.tran hello.tran winapi.tran mswhello.tran \ makehello.py elfdump.py all: Index: hello.tran =================================================================== RCS file: /cvsroot/wisp/wisp/users/dig/hello.tran,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- hello.tran 16 Apr 2003 07:58:57 -0000 1.2 +++ hello.tran 17 May 2003 05:37:51 -0000 1.3 @@ -8,6 +8,7 @@ \ This file is intended to be processed using tran.py +include i80386 include ia32 \ main entry point Index: ia32.tran =================================================================== RCS file: /cvsroot/wisp/wisp/users/dig/ia32.tran,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- ia32.tran 17 May 2003 05:28:17 -0000 1.10 +++ ia32.tran 17 May 2003 05:37:51 -0000 1.11 @@ -6,9 +6,6 @@ \ \\\\ @(#) $Id$ -\ registers -:regs reg32 %eax %ecx %edx %ebx %esp %ebp %esi %edi ; - \ These are prefixes for 32-bit mode :[ ] $o16 #x66 b, ; :[ ] $o32 ; Index: mswhello.tran =================================================================== RCS file: /cvsroot/wisp/wisp/users/dig/mswhello.tran,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- mswhello.tran 17 May 2003 04:26:58 -0000 1.11 +++ mswhello.tran 17 May 2003 05:37:51 -0000 1.12 @@ -9,6 +9,7 @@ \ Don't forget to translate with -fpe include ia32 +include i80386 include winapi \ main entry point Index: tran-builtins =================================================================== RCS file: /cvsroot/wisp/wisp/users/dig/tran-builtins,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- tran-builtins 17 May 2003 05:08:44 -0000 1.10 +++ tran-builtins 17 May 2003 05:37:51 -0000 1.11 @@ -78,7 +78,7 @@ interpreter.state = record_state :regs|family - if Meaning.has_key(family): raise 'duplicate declaration', tok + if Meaning.has_key(family): raise 'duplicate declaration', family Register(current_register_family) f = Register(current_register_family) Meaning[family] = f Index: tran.py =================================================================== RCS file: /cvsroot/wisp/wisp/users/dig/tran.py,v retrieving revision 1.77 retrieving revision 1.78 diff -u -d -r1.77 -r1.78 --- tran.py 17 May 2003 05:08:44 -0000 1.77 +++ tran.py 17 May 2003 05:37:51 -0000 1.78 @@ -247,7 +247,6 @@ Regstack = [] Generic_Register = Register() -reggen = Generic_Register.child_generator() MA_PREFIX = 1 Meaning = {'reg': Generic_Register, |