[Wisp-cvs] wisp/users/dig tran.py,1.60,1.61

[<di...@us...>]

Update of /cvsroot/wisp/wisp/users/dig
In directory sc8-pr-cvs1:/tmp/cvs-serv32536

Modified Files:
	tran.py 
Log Message:
minor cleanup

Index: tran.py
===================================================================
RCS file: /cvsroot/wisp/wisp/users/dig/tran.py,v
retrieving revision 1.60
retrieving revision 1.61
diff -u -d -r1.60 -r1.61
--- tran.py	22 Apr 2003 15:44:21 -0000	1.60
+++ tran.py	22 Apr 2003 15:47:59 -0000	1.61
@@ -167,7 +167,7 @@
             except StopIteration: pass
     except StopIteration: pass
 
-def state_outer (tok):
+def outer_state (tok):
     global Regstack
     if isinstance(tok, Integer_Literal):
         Regstack.append(tok)
@@ -252,14 +252,14 @@
     newmac = []
     Meaning[name] = ('macro', newmac)
     current_recordee = newmac
-    def state_record (tok):
+    def record_state (tok):
         global current_recordee, State
         if tok == Semicolon:
-            State = state_outer
+            State = outer_state
             current_recordee = None
         else:
             current_recordee.append(tok)
-    State = state_record
+    State = record_state
 
 :regs|family
     if Meaning.has_key(family): raise 'duplicate declaration', tok
@@ -268,7 +268,7 @@
     Meaning[family] = 'simple', f
     Registers[f] = family
     current_register_index = 0
-    def state_regs (tok):
+    def regs_state (tok):
         global State, current_register_family, current_register_index
         if tok != Semicolon:
             if Meaning.has_key(tok): raise 'duplicate declaration', tok
@@ -277,10 +277,10 @@
             Registers[r] = tok
             current_register_index += 1
         else:
-            State = state_outer
+            State = outer_state
             current_register_family += 1
             current_register_index = None
-    State = state_regs
+    State = regs_state
 
 align int
     cursect.align(long(Regstack.pop()))
@@ -340,7 +340,7 @@
 
 current_recordee = None
 current_register_family = 0
-State = state_outer
+State = outer_state
 Registers = {Generic_Register: 'reg'} # for reverse translation
 
 def mainloop ():