VTracer is a family of subprojects which can be used as tools for solving various problems, arising during Verilog Testbench development.
The last tool in the sequence is called Vcosim, Verilog-Perl co-simulation platform. This platform enables interoperability between Verilog and Perl processes, and on-the-fly transferring of information between the 2 domains.
The current demo demonstrates Verilog interoperability with Perl, while the user may use the same platform with any other language along with Verilog (TCL, Python, C/C++ etc.).... read more
This release includes Verilog co-simulation environment (Vcosim).
The co-simulation environment uses TCP sockets protocol.
The demo consists of a simple Verilog Testbench (client side) and a Perl memory model (server side).
The server side may be implemented in another language (Perl, TCL, Python, C/C++ etc.).
This release includes Structural Verilog parser.
The parser analyzes Verilog netlist and returns information on design structure, logic cones, self-contained logic clouds, etc.
VTracer is a ASIC developer assistance tool. It analyzes VCD dump file created on a simulation, and performs many helpful tasks, including:
- comparing 2 different VCD files, each one produced by another simulation. Helpful for automatization of signals comparison;
- Creating stimuli file for a Testbench, based on a VCD produced by another Testbench. Helpful during Testbench development, integration of design cores into a complex SOC, etc.
- Automatic creation of signal pointers module. This new module can be easily integrated into a Testbench, and it proevs to be ver helpful for finding/analyzing all important signals without need for browsing the design hierarchy.... read more
New features in this release:
1. The whole VTracer verification loop is demonstrated:
- Native Testbench generates the reference VCD dump file;
- Verilog stimuli is generated from this VCD file;
- The stimuli fille feeds the device into the new Testbench; another VCD file is generated;
- The 2 VCD's are compared - verification loop is closed.
2. Website updated (http://VTracer.sf.net)
3. Documentation updated.... read more
Verilog designers spend hours comparing VCD traces of different simulations. For example, when integrating an ASIC core into a SoC, the 1st trace is produced by the core verification environment. The 2nd trace is produced by applying the same stimuli to the inputs of the core after integration. Verifying that the outputs produced by the 2 Testbenches may be a tedious process.
VTracer is the solution. Version 1.0 was currently released.... read more