VSYML is an automated symbolic simulator for VHDL designs.

Features

  • VHDL Symbolic Simulation
  • Automatic model extraction

Project Activity

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Categories

Simulation, Electronic Design Automation (EDA), Test and Measurement

License

GNU General Public License version 2.0 (GPLv2)

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VHDL Symbolic Simulator Web Site

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Additional Project Details

Languages

English

Intended Audience

Information Technology, Science/Research, Telecommunications Industry, Developers, Quality Engineers

User Interface

Console/Terminal, Command-line

Programming Language

OCaml (Objective Caml), VHDL/Verilog

Database Environment

XML-based, Flat-file

Related Categories

OCaml (Objective Caml) Simulation Software, OCaml (Objective Caml) Electronic Design Automation (EDA) Software, OCaml (Objective Caml) Test and Measurement Software, VHDL/Verilog Simulation Software, VHDL/Verilog Electronic Design Automation (EDA) Software, VHDL/Verilog Test and Measurement Software

Registered

2009-03-22
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