File	Date	Author	Commit
functions	2015-08-13	vladimir	[24fcf0] rtClockGray clock converting 64 bit counter to ...
lcd	2015-06-22	vladimir	[a0cb72] Added sexagesimal realtime clock mm:ss.mmm.uuu....
rtClockGray	2015-08-13	vladimir	[24fcf0] rtClockGray clock converting 64 bit counter to ...
rtClockSexagesimal	2015-08-13	vladimir	[24fcf0] rtClockGray clock converting 64 bit counter to ...
Makefile	2015-04-16	vladimir	[36fd2a] This project aims to create a very simple frame...
README	2015-06-22	vladimir	[a0cb72] Added sexagesimal realtime clock mm:ss.mmm.uuu....
impact.cmd	2015-04-16	vladimir	[36fd2a] This project aims to create a very simple frame...
vhdl_bench.prj	2015-08-13	vladimir	[24fcf0] rtClockGray clock converting 64 bit counter to ...
vhdl_bench.scr	2015-04-16	vladimir	[36fd2a] This project aims to create a very simple frame...
vhdl_bench.ucf	2015-06-22	vladimir	[a0cb72] Added sexagesimal realtime clock mm:ss.mmm.uuu....
vhdl_bench.ut	2015-04-16	vladimir	[36fd2a] This project aims to create a very simple frame...
vhdl_bench.vhd	2015-08-13	vladimir	[24fcf0] rtClockGray clock converting 64 bit counter to ...

Read Me

==INTRODUCTION==
This project aims to create a very simple framework for estimating the synthesizable footprint of VHDL modules.

==SOURCE FILES==
1. Makefile       - build rules
2. vhdl_bench.vhd - top level VHDL
3. vhdl_bench.scr - xst configuration file
4. vhdl_bench.prj - list of VHDL sources
5. vhdl_bench.ucf - simple constraints file pinout and timing
6. vhdl_bench.ut  - configuration file for bitgen tool
7. impact.cmd     - jtag programmer configuration file


==REPORTING USAGE STATISTICS==
1. vhdl_bench.srp - synthesis report
2. vhdl_bench_prepar.mrp - mapping report