VHDL 6510-core Code
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Fredrik
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Hardware: Altera DE10-Lite dev kit
Links:
https://www.altera.com/solutions/partners/partner-profile/terasic-inc-/board/de10-lite-board.html
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1021
https://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_PCB.pdf
https://xania.org/201405/jsbeeb-getting-the-timings-right-cpu
http://codebase64.org/doku.php?id=base:6510_instruction_timing
https://en.wikibooks.org/wiki/A-level_Computing/AQA/Computer_Components,_The_Stored_Program_Concept_and_the_Internet/Machine_Level_Architecture/The_Fetch%E2%80%93Execute_cycle_and_the_role_of_registers_within_it
https://www.robots.ox.ac.uk/~dwm/Courses/2CO_2014/2CO-N2.pdf
http://web.mit.edu/jhawk/mnt/ss.b/vice-0.12.0/doc/64doc
https://www.c64-wiki.com/wiki/Bank_Switching
ftp://www.zimmers.net/pub/cbm/firmware/computers/c64/C64_PLA_Dissected.pdf
https://www.digikey.com/eewiki/pages/viewpage.action?pageId=28278929
Project:
The first idea was to create a processor core in the FPGA and to get an example
the 6510 processor in the Vic64 was the goal. It appeared that this was a slightly
bigger challenge than I thought but the show will go on.
To be able to test the implementation there will also be a debug interface which
will make it possible to set memory from a terminal.
****************************************************************************************
DONE list:
* Has to set pixel color to show on screen. For now it is black background and black
font color. Hardcoded background and foreground in font generator.
-> Fixed, should work as intended, has to be verified
* Font generator too slow, has to be optimized...
-> Handle 1 byte (8 bits) at a time instead of read same data many times. Write to
video ram is done during "silent time" when no access to address/data bus is needed.
* Init process to clear set memory at start - fill video ram etc
-> Kind of done. Fills memory with test picture.
* Debug interface, implementation and verification.
-> UART now bounces RX data back to TX
* Font generator
* memory controller.
-> Verified that mem controller is passing correct data to the font gen
-> init is writing to the memory controller, font generator is reading. Correct result.
* Verification of the vga controller
-> Done. Delay of VGA_HS/VS compared to pixel on/off verified
-> Implementation of "INIT_DONE" to be able to wait for the display memory to be initialized
before start of output to display. Mostly to make the test phase easier.
* New uart parser implemented
* Updated DIV in uart since the system clock had to be changed from 150 to 100MHz
* Work with uart parser / debugprocess:
- Move read/write functionality from uartparser to debugprocess
- Add data buffer in debug process for read/write and increase r/w address space to
256 byte (255 bytes used, protocol supports 0-255)
- Validate read (all areas)
read >1 byte RAM
write >1 byte RAM
read 1 and >1 byte ROM
read 1 and >1 byte IO
write 1 and >1 byte IO
- Validate write (all areas)
* The VGA_HS/VS will probably has to be delayed to set the correct pixel. This can be
examined in testbenches but functionality is not yet added.
* Started with the core... All fetch cycles takes 1 clock fetch + 1 clock run. Some takes
several run steps. Rewrite mainFSM.
* Documented instructions
* Move microcode to a separate file.
* Memory controller has been updated. Now double speed compared to system. Reason
for this is to simulate SRAM.
* Add BASIC ROM module, address $A000-$BFFF in memory controller
* Add KERNEL ROM module, address $E000-$FFFF in memory controller
* Registers for I/O memory area has to be default values. Everything is reset to '0'.
-> Core is setting default values
* To solve following, make a try with 1 wait state in all modules using ordinary RAM
- TIMING ! !
- UNCONSTRAINED ! !
- INFERRED LATCHES ! !
- TEST CORE + TOP IN BENCH
> Timing solved by optimizing some code and set the system clock to 25MHz
> Unconstrained is somewhat constrained after previous change - no msg from quartus
anyway...
> Inferred latches are gone (it seems), but this will be addressed later again.
> Testing is a continous work
* Fix test program for ROM (compile and create hex-file, add to proj, read hex-file)
* IRQ is partly tested
* CIA1: pbOn, outMode, runMode, load and todIn has to be fixed. Most of the registers
remains too. Most of the work remains.
* Testbench VIC2
* core6510 ready signal is not done correct, redesign...
* FontGenerator is removed
* Update the debug interface. Currently it's not working with read/write memory.
* Add functionality in the arduino (or switch to some windows program) to download
HEX-files. Reason for this is to own assembler progs for testing the VIC
* NMI is tested.
* Sprite0 last pixel row is not visible on screen. Fixed
* Sprite7 is corrupt. Fixed
* Raster latch is allways set in VICE, never in FPGA. Fixed
* MMC is set in FPGA, not in VICE. Fixed
* MBC is set in VICE, not in FPGA. Fixed
* Implement reg D01E and D01F. Fixed
* Lightpen is set in FPGA, not in VICE. Fixed
* CIA2 has to be implemented. Fixed
* Undocumented opcodes (SLO, ANC, RLA, SRE, RRA, DCP, ASR, ARR, SAX, LAX, SBX, ISB, NOP)
* Verified opcodes (SBX, ASR, ANC, ISB, DCP, SLO, RLA, SRE, RRA, SAX, LAX, ARR, NOP)
* Tested games:
- AMC; Playable
- 1994_10yr_after_vision_mhi; Actually possible to play...
- GALACTIC EMPIRE; Works
* SBC/ADC: Flags updated
****************************************************************************************
BUGS:
* Test program does not react the same way as in VICE when exiting.
VICE: Try to make a BASIC program --> out of memory
FPGA: No problem to make a BASIC program
* Tested games:
- 10'TH FRAME_GAP; doesn't start
- 1942V1_MHI; not possible to start game, graphics ok though
- 1942V2_MHI; rolling graphics at start
- 1943V1_MHI; Bugs at smooth scroll. *** Seems like YSCROLL needs an update ***
Looks like it restarts over and over.
- 1944_MHI; Graphics not ok
- 1985_MHI; Starts ok but not possible w/o joystick
- 4by4.F4CG; Jams after start screen
- BOMB JACK II++; Jams
- BOMBJACK+_TAC; Jams
- DAREDEVIL DENNIS; Starts ok but not possible w/o joystick
- HARRIER ATTACK; Works in some way, but not possible w/o joystick(?)
- HOBGOBLIN; Jams
- Pac-man; not possible w/o joystick(?)
TODO list:
* Make a trap to visualize when CPU jammed.
* Implement some kind of load feature from debug interface (to replace floppy).
Why? To be able to run Wolfgang Lorenz tests in the automated way.
* Test VIC IRQ signal
* Test sprites 1-6
* Lightpen IRQ? Will never work as in the C64 anyway....
* Add a halt signal from debug process to the VIC. Could use the RES bit in control reg 2.
* Rename MOS6567, should be 6569 (or VIC-II...)
* Testbench HW IRQ / NMI
* Page boundary crossing has to be implemented for many op codes
* Testbench for testing number of cycles for the test program
* Change the address handling - now both high and low address bytes are touched
when changing address. Shall be changed in order to update first low byte, next
clock update the high byte. In case of a write - during low byte update read is
active, write active when high byte is updated. This would probably fix following
issues:
* Timing for several opcodes is not correct according to 64doc.
* The page-bug for (jmp) is not yet implemented
* Lots of microcodes added which is not in use. Some of the old ones too.
* Address Hi/Lo has to trade places in the debug protocol. Lo is first, Hi is second.
* Update TB_UartRxTx to handle uartParser commands
- Add commands to enter/exit screen mode (write to screen directly; i.e. terminal
functionality)
NOTE: To use a regular terminal, there will be need of a translation from ascii to
petscii (or what its called).
- Commands for read/write register values in the core, change ps, status etc.
* Add support for PS/2 keyboard
* Add hardware and modules to support audio (SID)
* Graphics memory in SDRAM
* Streching...? some peripherals takes more time to handle data.
