More bugs

Since I managed to implement the SDRAM controller I have been trying to debug the VIC-II and the CIA. It really helps with bigger ram buffers when running the signal analyzer. One of the problems now is that I realized that there is at least one bug in the debug process, which actually is a bit ironic. It looks like the debug interface tries to write to the memory just as the debugEnable goes low. I have to fix this somehow, but it made me see that there also are some known "features" (bugs) in the windows tool that I use for the keyboard and also download compiled programs (mostly test progs) to my FPGA.
This is both good and bad - good that I saw what bug I have but bad because I don't think I can trust my tools. So I made a new prioritization:
1. Correct the bug found in the debug interface
2. Implement a PS/2 module so I can use a dedicated keyboard.
3. Continue debugging the VIC and CIA modules.
4. The VIC module still doesn't look good. Have to simplify the code.

I also have the documentation to do...