Well, somebody's got to be first here!
I downloaded VeriWell a few days ago, and am (currently!) very impressed. However, I've got one slight niggle. I'm using the compiler for self-checking regression tests, which check the correctness of the input Verilog code by comparing the runtime output against a set of golden log files. This works with various different simulators.
The problem I've got with VeriWell is that there's a lot of 'stdout' output which can't be silenced - copyright messages, "lxt support compiled in" messages, compiler passes, that sort of thing. I've had a quick look at the code, and these can't be turned off without some hacking. Ideally, this would be done by a '-silent' option. I could instead ignore this output in my comparison scripts, but it's not pretty.
This is trivial to do, but I don't want to create my own version of the code, unless Elliot/Mark want to merge it back in. Or has someone already done this? Comments?
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