#2 Redeclared port error

[Mark Hummel]

module x(xyz);
output xyz;
reg a;
reg clk;
always @(posedge clk) begin
a <= xyz;
end
reg xyz;
initial begin
$monitor( "a=",a);
xyz = 1;
clk = 0;
#10 clk = 1;
end
endmodule