#16 Timescale differences between modules in same simulation

[Trevor Williams]

If two module files contain different timescale precisions (same timescale units), incorrect simulation results occur. Given the following code example:

`timescale 1 s / 1 ps

module main;

ts_module tsm();

initial begin
`ifdef DUMP
$dumpfile( "timescale2.6.vcd" );
$dumpvars( 0, main );
`endif
#10;
$finish;
end

endmodule

`timescale 1 s / 1 s

module ts_module;

reg a;

initial begin
a = 1'b0;
#1;
a = 1'b1;
#1;
a = 1'b0;
end

endmodule

The second and third assignments to "a" within the ts_module module are not executed (and reported in the VCD dumpfile).