#11 wire assignment is not correctly evaluated

closed
nobody
None
5
2008-05-22
2008-05-16
Mark Hummel
No

This could snippet should result in c = 0, however
the recursive assignment does not appear to be
correctly propagated.

module xyz;
wire [15:0] c;
assign c={c[14:0],1'b0};
initial begin
#10;
/*
* the output 'c' should not have any x's
*/
$displayb(c);
end

endmodule

Discussion

  • Mark Hummel

    Mark Hummel - 2008-05-16

    Logged In: YES
    user_id=1341514
    Originator: YES

    Note the output actually results in z's not x's.
    However the output is still wrong.

     
  • Mark Hummel

    Mark Hummel - 2008-05-22

    Logged In: YES
    user_id=1341514
    Originator: YES

    Fixed in checkin:
    Checking in src/exec.cc;
    /cvsroot/veriwell/veriwell/src/exec.cc,v <-- exec.cc
    new revision: 1.2; previous revision: 1.1
    done
    Checking in src/schedule.cc;
    /cvsroot/veriwell/veriwell/src/schedule.cc,v <-- schedule.cc
    new revision: 1.2; previous revision: 1.1
    done
    Checking in src/schedule.h;
    /cvsroot/veriwell/veriwell/src/schedule.h,v <-- schedule.h
    new revision: 1.2; previous revision: 1.1
    done

     
  • Mark Hummel

    Mark Hummel - 2008-05-22
    • status: open --> closed
     

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