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vba-commit
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From: Pokemonhacker <pok...@us...> - 2004-11-19 01:08:47
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Update of /cvsroot/vba/VisualBoyAdvance/src In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv5619 Modified Files: arm-new.h thumb.h Log Message: - fixed some instruction having incorrect cycles (caused SDL debugger to skip several instructions) Index: arm-new.h =================================================================== RCS file: /cvsroot/vba/VisualBoyAdvance/src/arm-new.h,v retrieving revision 1.13 retrieving revision 1.14 diff -C2 -d -r1.13 -r1.14 *** arm-new.h 9 Nov 2004 16:07:51 -0000 1.13 --- arm-new.h 19 Nov 2004 01:08:32 -0000 1.14 *************** *** 1114,1117 **** --- 1114,1118 ---- u32 value;\ \ + clockTicks++;\ if(shift) {\ LOGICAL_LSL_REG\ *************** *** 1151,1154 **** --- 1152,1156 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_LSR_REG\ *************** *** 1190,1193 **** --- 1192,1196 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_ASR_REG\ *************** *** 1234,1237 **** --- 1237,1241 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_ROR_REG\ *************** *** 1265,1269 **** {\ /* OP Rd,Rb,Rm LSL Rs */\ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 1269,1273 ---- {\ /* OP Rd,Rb,Rm LSL Rs */\ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 1310,1314 **** {\ /* OP Rd,Rb,Rm LSR Rs */ \ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 1314,1318 ---- {\ /* OP Rd,Rb,Rm LSR Rs */ \ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 1355,1359 **** {\ /* OP Rd,Rb,Rm ASR Rs */ \ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 1359,1363 ---- {\ /* OP Rd,Rb,Rm ASR Rs */ \ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 1402,1406 **** {\ /* OP Rd,Rb,Rm ROR Rs */\ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 1406,1410 ---- {\ /* OP Rd,Rb,Rm ROR Rs */\ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 1465,1468 **** --- 1469,1473 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_ROR_IMM\ *************** *** 1503,1506 **** --- 1508,1512 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ \ if(shift) {\ *************** *** 1540,1543 **** --- 1546,1550 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_LSR_REG\ *************** *** 1578,1581 **** --- 1585,1589 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_ASR_REG\ *************** *** 1621,1624 **** --- 1629,1633 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_ROR_REG\ *************** *** 1652,1656 **** {\ /* OP Rd,Rb,Rm LSL Rs */\ ! clockTicks++;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ --- 1661,1665 ---- {\ /* OP Rd,Rb,Rm LSL Rs */\ ! clockTicks+=2;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ *************** *** 1696,1700 **** {\ /* OP Rd,Rb,Rm LSR Rs */ \ ! clockTicks++;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ --- 1705,1709 ---- {\ /* OP Rd,Rb,Rm LSR Rs */ \ ! clockTicks+=2;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ *************** *** 1740,1744 **** {\ /* OP Rd,Rb,Rm ASR Rs */ \ ! clockTicks++;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ --- 1749,1753 ---- {\ /* OP Rd,Rb,Rm ASR Rs */ \ ! clockTicks+=2;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ *************** *** 1786,1790 **** {\ /* OP Rd,Rb,Rm ROR Rs */\ ! clockTicks++;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ --- 1795,1799 ---- {\ /* OP Rd,Rb,Rm ROR Rs */\ ! clockTicks+=2;\ int shift = reg[(opcode >> 8)&15].B.B0;\ int dest = (opcode>>12) & 15;\ *************** *** 1847,1850 **** --- 1856,1860 ---- bool C_OUT = C_FLAG;\ u32 value;\ + clockTicks++;\ if(shift) {\ LOGICAL_ROR_IMM\ *************** *** 1885,1888 **** --- 1895,1899 ---- int dest = (opcode>>12) & 15;\ u32 value;\ + clockTicks++;\ if(shift) {\ ARITHMETIC_LSL_REG\ *************** *** 1921,1924 **** --- 1932,1936 ---- int dest = (opcode>>12) & 15;\ u32 value;\ + clockTicks++;\ if(shift) {\ ARITHMETIC_LSR_REG\ *************** *** 1957,1960 **** --- 1969,1973 ---- int dest = (opcode>>12) & 15;\ u32 value;\ + clockTicks++;\ if(shift) {\ ARITHMETIC_ASR_REG\ *************** *** 1995,1998 **** --- 2008,2012 ---- int dest = (opcode>>12) & 15;\ u32 value;\ + clockTicks++;\ if(shift) {\ ARITHMETIC_ROR_REG\ *************** *** 2031,2034 **** --- 2045,2049 ---- int dest = (opcode>>12) & 15;\ u32 value;\ + clockTicks++;\ if(shift) {\ if(shift == 32) {\ *************** *** 2066,2070 **** {\ /* OP Rd,Rb,Rm LSR Rs */\ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 2081,2085 ---- {\ /* OP Rd,Rb,Rm LSR Rs */\ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 2106,2110 **** {\ /* OP Rd,Rb,Rm ASR Rs */\ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 2121,2125 ---- {\ /* OP Rd,Rb,Rm ASR Rs */\ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 2148,2152 **** {\ /* OP Rd,Rb,Rm ROR Rs */\ ! clockTicks++;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ --- 2163,2167 ---- {\ /* OP Rd,Rb,Rm ROR Rs */\ ! clockTicks+=2;\ int base = (opcode >> 16) & 0x0F;\ int shift = reg[(opcode >> 8)&15].B.B0;\ *************** *** 2207,2210 **** --- 2222,2226 ---- int dest = (opcode >> 12) & 0x0F;\ u32 value;\ + clockTicks++;\ {\ ARITHMETIC_ROR_IMM\ *************** *** 3199,3202 **** --- 3215,3219 ---- // MRS Rd, CPSR // TODO: check if right instruction.... + clockTicks++; CPUUpdateCPSR(); reg[(opcode >> 12) & 0x0F].I = reg[16].I; *************** *** 3209,3212 **** --- 3226,3230 ---- CPUWriteMemory(address, reg[opcode&15].I); reg[(opcode >> 12) & 15].I = temp; + clockTicks++; } break; *************** *** 3232,3235 **** --- 3250,3254 ---- reg[16].I = newValue; CPUUpdateFlags(); + clockTicks++; if(!armState) { // this should not be allowed, but it seems to work THUMB_PREFETCH; *************** *** 3263,3266 **** --- 3282,3286 ---- // TODO: check if right instruction... reg[(opcode >> 12) & 0x0F].I = reg[17].I; + clockTicks++; break; case 0x149: *************** *** 3271,3274 **** --- 3291,3295 ---- CPUWriteByte(address, reg[opcode&15].B.B0); reg[(opcode>>12)&15].I = temp; + clockTicks++; } break; *************** *** 3288,3291 **** --- 3309,3313 ---- reg[17].I = (reg[17].I & 0x00FFFFFF) | (value & 0xFF000000); } + clockTicks++; } break; *************** *** 3352,3355 **** --- 3374,3378 ---- reg[15].I = armNextPC + 2; } + clockTicks++; } break; *************** *** 3387,3390 **** --- 3410,3414 ---- reg[17].I = (reg[17].I & 0x00FFFFFF) | (value & 0xFF000000); } + clockTicks++; } break; Index: thumb.h =================================================================== RCS file: /cvsroot/vba/VisualBoyAdvance/src/thumb.h,v retrieving revision 1.12 retrieving revision 1.13 diff -C2 -d -r1.12 -r1.13 *** thumb.h 15 Sep 2004 22:12:52 -0000 1.12 --- thumb.h 19 Nov 2004 01:08:32 -0000 1.13 *************** *** 2273,2277 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2273,2277 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2283,2287 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2283,2287 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2293,2297 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2293,2297 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2303,2307 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2303,2307 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2313,2317 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2313,2317 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2323,2327 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2323,2327 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2333,2337 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2333,2337 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2343,2347 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2343,2347 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2353,2357 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2353,2357 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2363,2367 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2363,2367 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2373,2377 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2373,2377 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2383,2387 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2383,2387 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2393,2397 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2393,2397 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; *************** *** 2403,2407 **** reg[15].I += 2; THUMB_PREFETCH; ! clockTicks = 3; } break; --- 2403,2407 ---- reg[15].I += 2; THUMB_PREFETCH; ! clockTicks += 2; } break; |
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