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From: Zhiyao T. <mc...@gm...> - 2006-10-12 02:09:21
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Hi, I planed to use cachegrind tool to profile the instruction and data cache usage in my program. When I startup it with default options "valgrind --tool=cachegrind MyProgram", it shows following information at the beginning: ...... --11725-- warning: Unknown Intel cache config value (0xB1), ignoring --11725-- warning: Unknown Intel cache config value (0x5), ignoring --11725-- warning: Unknown Intel cache config value (0xF0), ignoring --11725-- warning: Unknown Intel cache config value (0x57), ignoring --11725-- warning: Unknown Intel cache config value (0x56), ignoring --11725-- warning: Unknown Intel cache config value (0x49), ignoring --11725-- warning: Unknown Intel cache config value (0xB4), ignoring --11725-- warning: L2 cache not installed, ignore L2 results. ...... The valgrind I used is valgrind-3.2.0-Debian. Seems that it can't recognize the CPU cache config. Shall I specified the I1/D1/L2 options directly in command line? If so, what values to use? According to the content of /proc/cpuinfo, my box has 4 CPUs, every one is like this: processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Xeon(R) CPU 5130 @ 2.00GHz stepping : 6 cpu MHz : 1994.999 cache size : 4096 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 2 fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl vmx tm2 cx16 xtpr lahf_lm bogomips : 3993.78 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: Thanks a lot |
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From: Nicholas N. <nj...@cs...> - 2006-10-12 02:27:43
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On Thu, 12 Oct 2006, Zhiyao Tu wrote: > Hi, > > I planed to use cachegrind tool to profile the instruction and data > cache usage in my program. When I startup it with default options > "valgrind --tool=cachegrind MyProgram", it shows following information > at the beginning: > > ...... > --11725-- warning: Unknown Intel cache config value (0xB1), ignoring > --11725-- warning: Unknown Intel cache config value (0x5), ignoring > --11725-- warning: Unknown Intel cache config value (0xF0), ignoring > --11725-- warning: Unknown Intel cache config value (0x57), ignoring > --11725-- warning: Unknown Intel cache config value (0x56), ignoring > --11725-- warning: Unknown Intel cache config value (0x49), ignoring > --11725-- warning: Unknown Intel cache config value (0xB4), ignoring > --11725-- warning: L2 cache not installed, ignore L2 results. > ...... > > The valgrind I used is valgrind-3.2.0-Debian. Seems that it can't > recognize the CPU cache config. Shall I specified the I1/D1/L2 options > directly in command line? Yes! > If so, what values to use? According to the > content of /proc/cpuinfo, my box has 4 CPUs, every one is like this: > > cache size : 4096 KB I think that's the L2 size. As for the I1/D1, I don't know, you could try googling for it. Ultimately due to various approximations Cachegrind's results are not exact -- you're unlikely to get them closely matching results from hardware counters, for example. Instead, think of Cachegrind's results as giving you an idea of your program's cache behaviour in general, in which case it doesn't matter if the cache configuration doesn't match reality exactly. Nick |
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From: Julian S. <js...@ac...> - 2006-10-12 02:52:40
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> directly in command line? If so, what values to use? According to the > content of /proc/cpuinfo, my box has 4 CPUs, every one is like this: Assuming this is a Pentium 4 based Xeon, and not a Core 2 one, you should specify I1 of 16k, D1 of 16k and L2 of 4096k. It would be helpful to know what CPU this really is. J |
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From: Zhiyao T. <mc...@gm...> - 2006-10-12 04:20:14
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Hi Julian, Thanks for your information. I searched and found the CPU is this one: Dual Core Intel(r) Xeon(r) processor 5130 Dual Core Intel(r) Xeon(r) processor 5100 Series (2.00GHz, 4MB L2 Cache, 1333MHz FSB, 65W, LGA771) 2006/10/12, Julian Seward <js...@ac...>: > > > directly in command line? If so, what values to use? According to the > > content of /proc/cpuinfo, my box has 4 CPUs, every one is like this: > > Assuming this is a Pentium 4 based Xeon, and not a Core 2 one, you > should specify I1 of 16k, D1 of 16k and L2 of 4096k. > > It would be helpful to know what CPU this really is. > > J > |
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From: Josef W. <Jos...@gm...> - 2006-10-12 08:35:58
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On Thursday 12 October 2006 06:20, Zhiyao Tu wrote: > Hi Julian, >=20 > Thanks for your information. >=20 > I searched and found the CPU is this one: >=20 > Dual Core Intel(r) Xeon(r) processor 5130 > Dual Core Intel(r) Xeon(r) processor 5100 Series (2.00GHz, 4MB L2 > Cache, 1333MHz FSB, 65W, LGA771) That is a Core 2 Duo (Woodcrest). As I have such a machine around to test, I think I can come up with a patch. Actually, I get exactly the same warnings. According to table 3.17 of the "Intel 64 and IA-32 Architectures Software Developer=E2=80=99s Manual, Volume 2A, Revision 21": (see http://www.intel.com/design/pentium4/manuals/index_new.htm) > ...... > --11725-- warning: Unknown Intel cache config value (0xB1), ignoring Not specified (?). However, B0 talks about instruction TLB, which is uninteresting for Cachegrind. > --11725-- warning: Unknown Intel cache config value (0x5), ignoring Data TLB1: 4 MByte pages, 4-way set associative, 32 entries Uninteresting for Cachegrind. > --11725-- warning: Unknown Intel cache config value (0xF0), ignoring 64-Byte prefetching. Hmm... No idea about that. > --11725-- warning: Unknown Intel cache config value (0x57), ignoring Data TLB0: 4 KByte pages, 4-way associative, 16 entries Uninteresting for Cachegrind. > --11725-- warning: Unknown Intel cache config value (0x56), ignoring Data TLB0: 4 MByte pages, 4-way set associative, 16 entries Uninteresting for Cachegrind. > --11725-- warning: Unknown Intel cache config value (0x49), ignoring 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size Important for Cachegrind: L2 cache size of 4 MB. > --11725-- warning: Unknown Intel cache config value (0xB4), ignoring Data TLB1: 4 KByte pages, 4-way associative, 256 entries Uninteresting for Cachegrind. > --11725-- warning: L2 cache not installed, ignore L2 results. Wow. I did not known that Cachegrind produces such warnings. However, in this case we have a L2 cache with 4MB (see above). Josef |
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From: Nicholas N. <nj...@cs...> - 2006-10-12 09:03:12
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On Thu, 12 Oct 2006, Josef Weidendorfer wrote: > According to table 3.17 of the "Intel 64 and IA-32 Architectures > Software Developer=FF=FFs Manual, Volume 2A, Revision 21": > (see http://www.intel.com/design/pentium4/manuals/index_new.htm) > >> ...... >> --11725-- warning: Unknown Intel cache config value (0xB1), ignoring > > Not specified (?). > However, B0 talks about instruction TLB, which is uninteresting for > Cachegrind. > >> --11725-- warning: Unknown Intel cache config value (0x5), ignoring > > Data TLB1: 4 MByte pages, 4-way set associative, 32 entries > Uninteresting for Cachegrind. > >> --11725-- warning: Unknown Intel cache config value (0xF0), ignoring > > 64-Byte prefetching. > Hmm... No idea about that. > >> --11725-- warning: Unknown Intel cache config value (0x57), ignoring > > Data TLB0: 4 KByte pages, 4-way associative, 16 entries > Uninteresting for Cachegrind. > >> --11725-- warning: Unknown Intel cache config value (0x56), ignoring > > Data TLB0: 4 MByte pages, 4-way set associative, 16 entries > Uninteresting for Cachegrind. > >> --11725-- warning: Unknown Intel cache config value (0x49), ignoring > > 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size > Important for Cachegrind: L2 cache size of 4 MB. > >> --11725-- warning: Unknown Intel cache config value (0xB4), ignoring > > Data TLB1: 4 KByte pages, 4-way associative, 256 entries > Uninteresting for Cachegrind. > >> --11725-- warning: L2 cache not installed, ignore L2 results. > > Wow. I did not known that Cachegrind produces such warnings. > However, in this case we have a L2 cache with 4MB (see above). Can you create a patch to fix this? (Is the CPUID code identical in=20 Callgrind compared to Cachegrind?) That would be really helpful! Nick |
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From: Josef W. <Jos...@gm...> - 2006-10-12 10:16:27
Attachments:
cg.patch
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On Thursday 12 October 2006 11:02, Nicholas Nethercote wrote: > Can you create a patch to fix this? Patch attached. Comment would be something like: "Cachegrind: Update cache parameter detection according to revision 21 of Intels Software Developer Manual" I also added some old addittions from cg-x86.c to cg-amd64.c. > (Is the CPUID code identical in > Callgrind compared to Cachegrind?) That would be really helpful! Yes. See callgrind/Makefile.am: ... CALLGRIND_SOURCES_X86 = ../cachegrind/cg-x86.c CALLGRIND_SOURCES_AMD64 = ../cachegrind/cg-amd64.c ... Probably should be backported. > > Nick |
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From: Julian S. <js...@ac...> - 2006-10-12 12:01:48
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> Patch attached. Comment would be something like: Cool. Can you commit it and also add an entry to 3_2_BUGSTATUS.txt? J |
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From: Nicholas N. <nj...@cs...> - 2006-10-12 12:58:52
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On Thu, 12 Oct 2006, Josef Weidendorfer wrote: > I also added some old addittions from cg-x86.c to cg-amd64.c. Do we need separate x86 and AMD64 files? Those two files are almost identical... Nick |
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From: Josef W. <Jos...@gm...> - 2006-10-12 13:55:31
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On Thursday 12 October 2006 14:58, Nicholas Nethercote wrote: > On Thu, 12 Oct 2006, Josef Weidendorfer wrote: > > > I also added some old addittions from cg-x86.c to cg-amd64.c. > > Do we need separate x86 and AMD64 files? Those two files are almost > identical... Hmm.. In general, the way how to automatically detect cache sizes is architecture dependent. However, in this case, the results from CPUID seem to have the same interpretation at least for Intel chips. IMHO, we should move common parts into a cg-x86-amd64-common.c, and include this both from cg-x86.c and cg-amd64.c. Josef |