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From: Wan M. F. W. I. <wan...@mc...> - 2011-02-18 15:21:36
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Hi, Do cachegrind use the same cache model for different processors? (eg. x86, armv7-a8, armv7-a9, etc). Thanks, Kind regards, -- Wan Mohd Fairuz WAN ISMAIL |
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From: Josef W. <Jos...@gm...> - 2011-02-18 19:15:00
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On Friday 18 February 2011, Wan Mohd Fairuz Wan Ismail wrote: > Hi, > Do cachegrind use the same cache model for different processors? (eg. x86, > armv7-a8, armv7-a9, etc). Yes. 2 levels (L1 separate for I/D, the other unified), inclusive, synchronous, LRU replacement. Only parameters are adapted to current processor: size, line size, associatvity. If a processor has 3 levels, parameters of L1 and L3 are actually used. This model actually is most near to Intel processors, but it always was just an approximation. Especially it is not simulating the AMD processor exclusive caches (where L2/L3 are victim caches). The idea of this simple model is not to be as near as possible to real hardware, but to highlight common problems of an application regarding cache behavior, such that the code afterwards would run faster on every architecture using caches. Do you see a need for more exact models? Josef > > Thanks, > Kind regards, > |
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From: Wan M. F. W. I. <wan...@mc...> - 2011-02-21 18:23:18
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Hi, I think it's necessary to have an approximate model for each processor (ARM, PowerPC, etc) since their cache models are different. It might be a good idea if we can have a better flexibility to use the tool ( eg: the choice of replacement policy). From what I see, eventhough the tool itself has been ported to arm, but the cache model used is still x86's. Kind regards, Fairuz On Fri, Feb 18, 2011 at 8:14 PM, Josef Weidendorfer < Jos...@gm...> wrote: > On Friday 18 February 2011, Wan Mohd Fairuz Wan Ismail wrote: > > Hi, > > Do cachegrind use the same cache model for different processors? (eg. > x86, > > armv7-a8, armv7-a9, etc). > > Yes. 2 levels (L1 separate for I/D, the other unified), inclusive, > synchronous, LRU replacement. > Only parameters are adapted to current processor: size, line size, > associatvity. > If a processor has 3 levels, parameters of L1 and L3 are actually used. > > This model actually is most near to Intel processors, but it always was > just > an approximation. Especially it is not simulating the AMD processor > exclusive > caches (where L2/L3 are victim caches). > > The idea of this simple model is not to be as near as possible to real > hardware, > but to highlight common problems of an application regarding cache > behavior, such > that the code afterwards would run faster on every architecture using > caches. > > Do you see a need for more exact models? > > Josef > > > > > > Thanks, > > Kind regards, > > > > > -- Wan Mohd Fairuz WAN ISMAIL Masters in Electronics Engineering, Majoring in Embedded System Engineering, Polytech Nice Sophia Antipolis, FRANCE. +33(0)643461339 +60172071591 15 Le Palais des Fleurs, 74 Boulevard Raymond Poincare, 06160 Juan les Pins, FRANCE. http://www.watt.com.my |
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From: Josef W. <Jos...@gm...> - 2011-03-01 15:53:10
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On Monday 21 February 2011, Wan Mohd Fairuz Wan Ismail wrote: > I think it's necessary to have an approximate model for each processor (ARM, > PowerPC, etc) since their cache models are different. It might be a good > idea if we can have a better flexibility to use the tool ( eg: the choice of > replacement policy). From what I see, eventhough the tool itself has been > ported to arm, but the cache model used is still x86's. Hmm.. perhaps the key is to make it easy to adapt the simulator code to your own needs, instead of providing multiple models, which still do not fit everybody's needs. Anyway: I think that support for ARMs pseudo-random replacement strategy for L1 (is this correct?) would be nice to have. You could create a "wishlist" bug report and attach your patch for that. Thanks, Josef |