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From: janjust <tja...@un...> - 2013-08-22 19:58:28
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Hi, If certain instructions are not detected through configure process, does that imply that a valgrind build will not be configured to handle these instructions (i.e. fail at runtime)? I have a system where my host nodes are somewhat different from my target nodes (where the valgrind package will run) and I'm running into unhandled instructions when running applications. I don't know if these instructions are not supported because configure doesn't detect them during configure, or if they truly are not - implemented? Certain instructions that are not detected are AVX2 and BMI1/2, BUT, I'm not sure if these are the culprits of unhandled instructions. I think I saw a patch committed that handles these instructions. checking if x86/amd64 assembler speaks AVX2... no checking if x86/amd64 assembler speaks BMI1 and BMI2... no I'm positive that my target node has them (AMD bulldozer/piledriver). But again, if I try to compile the code snippets generated during ./configure process it exits with the same error. So this leaves me even more confused: is this a compiler/assembler issue (am I missing a flag?), or an architecture issue. Moreover, I don't really know which instructions are causing it to fail, how do I check? The line I get is: 21 vex amd64->IR: unhandled instruction bytes: 0xC4 0xE3 0xF1 0x6B 0x15 0x12 0x4 0x0 22 vex amd64->IR: REX=0 REX.W=1 REX.R=0 REX.X=0 REX.B=0 23 vex amd64->IR: VEX=1 VEX.L=0 VEX.nVVVV=0x1 ESC=0F3A 24 vex amd64->IR: PFX.66=1 PFX.F2=0 PFX.F3=0 25 3=0 Can anyone clarify? P.S. If you need more clarification regarding my system/compiler/os let me know. For what it's worth, it's a cray system composed of bulldozer/piledriver CPUs, and the OS is cray CNL. -- View this message in context: http://valgrind.10908.n7.nabble.com/question-on-valgrind-s-configure-and-build-process-tp46406.html Sent from the Valgrind - Users mailing list archive at Nabble.com. |
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From: Tom H. <to...@co...> - 2013-08-22 20:34:29
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On 22/08/13 20:58, janjust wrote: > If certain instructions are not detected through configure process, does > that imply that a valgrind build will not be configured to handle these > instructions (i.e. fail at runtime)? No - those tests mostly only govern which bits of the test suite will be built and run. The actual emulation engine checks at run time which instructions are supported. > 21 vex amd64->IR: unhandled instruction bytes: 0xC4 0xE3 0xF1 0x6B 0x15 0x12 > 0x4 0x0 > 22 vex amd64->IR: REX=0 REX.W=1 REX.R=0 REX.X=0 REX.B=0 > 23 vex amd64->IR: VEX=1 VEX.L=0 VEX.nVVVV=0x1 ESC=0F3A > 24 vex amd64->IR: PFX.66=1 PFX.F2=0 PFX.F3=0 > 25 3=0 That (in effect 66 0F 3A 6B) appears to be undefined in the latest Intel manual so I'm guessing it's some AMD extension... That said it doesn't seem to be defined in the AMD manual either which is a little confusing... Tom -- Tom Hughes (to...@co...) http://compton.nu/ |
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From: janjust <tja...@un...> - 2013-08-22 21:16:41
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I forgot to mention that I used a pgi compiler in the previous run, if I swap my modules and use a gnu compiler environment it still breaks but this time the unhandled instruction bytes are a different: I'm not sure sure if the significance of this other than unhandled instructions? 19 vex amd64->IR: unhandled instruction bytes: vex amd64->IR: unhandled instruction bytes: 0x8F 0xE8 0x78 0xA2 0xC1 0x40 0xC5 0xFB 20 vex amd640 21 vex amd64->IR: VEX=0 VEX.L=0 VEX.nVVVV=0x 22 vex amd64 23 vex amd64->IR: PFX.66=0 PFX.F2=0 PFX.F3=0 24 vex amd64->IR: PFX.66=0 PFX.F2=0 PFX.F3=0 25 3=0 26 vex amd64->IR: unhandled instruction bytes: 0x8F 0xE8 0x78 0xA2 0xC1 0x40 0xC5 0xFB 27 vex amd64->IR: REX=0 REX.W=0 REX.R=0 REX.X=0 REX.B=0 28 vex amd64->IR: VEX=0 VEX.L=0 VEX.nVVVV=0x0 ESC=NONE 29 vex amd64->IR: PFX.66=0 PFX.F2=0 PFX.F3=0 30 ==19226== valgrind: Unrecognised instruction at address 0x402ed7. 31 ==19228== valgrind: Unrecognised instruction at address 0x402ed7. 32 vex amd64->IR: unhandled instruction bytes: 0x8F 0xE8 0x78 0xA2 0xC1 0x40 0xC5 0xFB 33 vex amd64->IR: REX=0 REX.W=0 REX.R=0 REX.X=0 REX.B=0 34 vex amd64->IR: VEX=0 VEX.L=0 VEX.nVVVV=0x0 ESC=NONE 35 vex amd64->IR: PFX.66=0 PFX.F2=0 PFX.F3=0 -Tommy -- View this message in context: http://valgrind.10908.n7.nabble.com/question-on-valgrind-s-configure-and-build-process-tp46406p46408.html Sent from the Valgrind - Users mailing list archive at Nabble.com. |
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From: Tom H. <to...@co...> - 2013-08-22 21:30:17
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On 22/08/13 22:16, janjust wrote: > 19 vex amd64->IR: unhandled instruction bytes: vex amd64->IR: unhandled > instruction bytes: 0x8F 0xE8 0x78 0xA2 0xC1 0x40 0xC5 0xFB That's a XOP instruction which is an AMD specific extension that I don't believe valgrind currently supports. See: http://en.wikipedia.org/wiki/XOP_instruction_set Tom -- Tom Hughes (to...@co...) http://compton.nu/ |