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From: Jain, K. <kee...@cr...> - 2011-02-11 17:13:27
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Dear All, Can anyone let me know that can calgrind/cachegrind is able to simulate the Nehalem(Intel Xeon 54xx/55xx) cache architecture? As Nehalem has a large L2 cache. With regards, Keerti =============================================================================== Please access the attached hyperlink for an important electronic communications disclaimer: http://www.credit-suisse.com/legal/en/disclaimer_email_ib.html =============================================================================== |
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From: Josef W. <Jos...@gm...> - 2011-02-11 18:19:56
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On Friday 11 February 2011, Jain, Keerti wrote: > Can anyone let me know that can calgrind/cachegrind is able to simulate > the Nehalem(Intel Xeon 54xx/55xx) cache architecture? > As Nehalem has a large L2 cache. I do not see the connection between your question and that statement. Cache hierarchies in real processors are quite more complex than the cache model of Callgrind/Cachegrind (e.g. they work asynchronous, with multiple loads on the fly, and have a kinds of prefetchers doing future access predictions). Thus, this is always only an approximation. Nehalem has 3 cache levels. Private L1I,L1D and L2 per core, and shared L3. Callgrind/Cachegrind always simulate 2 levels only. When it detects a processor with 3 levels, it uses the parameters for L1 and L3. So, what you miss is how many of the L1 misses actually are L2 hits. But L1 hits/misses and LL misses should be reasonable approximations to Nehalems behaviour. The latter (main memory accesses) matters most for performance. Josef > > With regards, > Keerti > > =============================================================================== > Please access the attached hyperlink for an important electronic communications disclaimer: > http://www.credit-suisse.com/legal/en/disclaimer_email_ib.html > =============================================================================== > > |