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From: Junchang W. <jun...@gm...> - 2008-09-09 14:12:06
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Dear Sir. I'm using valgrind in our sever equipped with Intel Core 2 Quad processor. The size of L2 cache is 6M. wangjc@pesc8:~/project/cct$ cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 23 model name : Intel(R) Xeon(R) CPU E5410 @ 2.33GHz stepping : 6 cpu MHz : 2327.500 cache size : 6144 KB physical id : 0 siblings : 4 core id : 0 cpu cores : 4 fpu : yes fpu_exception : yes cpuid level : 10 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr dca sse4_1 lahf_lm bogomips : 4657.69 clflush size : 64 cache_alignment : 64 address sizes : 38 bits physical, 48 bits virtual power management: ...... I tried naively running valgrind like this, wangjc@pesc8:~/project/cct$ valgrind --tool=cachegrind ./a.out and got following warnings, --8726-- warning: Unknown Intel cache config value (0x4e), ignoring --8726-- warning: L2 cache not installed, ignore L2 results. Then, I tried running vagrind with a specific L2 cache wangjc@pesc8:~/project/cct$ valgrind --tool=cachegrind --L2=6291456,16,64 ./a.out and got following warnings, --8818-- warning: Unknown Intel cache config value (0x4e), ignoring --8818-- warning: L2 cache not installed, ignore L2 results. ==8818== error: L2 size of 6291456B not a power of two; aborting. I have checked Valgrind User Manual and the doc said it is not particularly hard to write my own cache simulator. But I failed to find more useful messages about this topic. How can I write a simulator by myself? Is there a short-circuited method? Thank you very much in advance. Junchang |
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From: Julian S. <js...@ac...> - 2008-09-09 15:08:02
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> Then, I tried running vagrind with a specific L2 cache > wangjc@pesc8:~/project/cct$ valgrind --tool=cachegrind --L2=6291456,16,64 > ./a.out > and got following warnings, > --8818-- warning: Unknown Intel cache config value (0x4e), ignoring > --8818-- warning: L2 cache not installed, ignore L2 results. > ==8818== error: L2 size of 6291456B not a power of two; aborting. > > I have checked Valgrind User Manual and the doc said it is not particularly > hard to write my own cache simulator. But I failed to find more useful > messages about this topic. How can I write a simulator by myself? Well, I don't know the details of Cachegrind's cache simulator. But you should at least be able to make progress by selecting a power of 2 cache size, eg --L2=4194304,16,64. J |
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From: Junchang W. <jun...@gm...> - 2008-09-10 00:42:26
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Hi Julian, Thank you very much for this suggestion. And it works. But the real size of L2 cache in my sever is 6M. Can Cachegrind support 6M L2 cache? On Tue, Sep 9, 2008 at 10:57 PM, Julian Seward <js...@ac...> wrote: > > > Then, I tried running vagrind with a specific L2 cache > > wangjc@pesc8:~/project/cct$ valgrind --tool=cachegrind > --L2=6291456,16,64 > > ./a.out > > and got following warnings, > > --8818-- warning: Unknown Intel cache config value (0x4e), ignoring > > --8818-- warning: L2 cache not installed, ignore L2 results. > > ==8818== error: L2 size of 6291456B not a power of two; aborting. > > > > I have checked Valgrind User Manual and the doc said it is not > particularly > > hard to write my own cache simulator. But I failed to find more useful > > messages about this topic. How can I write a simulator by myself? > > Well, I don't know the details of Cachegrind's cache simulator. But you > should at least be able to make progress by selecting a power of 2 > cache size, eg --L2=4194304,16,64. > > J > |
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From: Julian S. <js...@ac...> - 2008-09-10 07:26:02
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On Wednesday 10 September 2008, Junchang Wang wrote: > Hi Julian, > Thank you very much for this suggestion. And it works. > > But the real size of L2 cache in my sever is 6M. Can Cachegrind support 6M > L2 cache? No. Not at the moment. But maybe it does not matter: even if you simulate a 4M cache, you will find out which part(s) of your algorithms cause many cache misses and which are ok. J |