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From: <sv...@va...> - 2009-08-28 22:34:23
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Author: sewardj Date: 2009-08-28 23:34:09 +0100 (Fri, 28 Aug 2009) New Revision: 10878 Log: Add support for the L2 cache on Intel T4200. Modified: trunk/cachegrind/cg-x86-amd64.c Modified: trunk/cachegrind/cg-x86-amd64.c =================================================================== --- trunk/cachegrind/cg-x86-amd64.c 2009-08-28 16:25:20 UTC (rev 10877) +++ trunk/cachegrind/cg-x86-amd64.c 2009-08-28 22:34:09 UTC (rev 10878) @@ -38,7 +38,7 @@ #include "cg_arch.h" -// All CPUID info taken from sandpile.org/a32/cpuid.htm */ +// All CPUID info taken from sandpile.org/ia32/cpuid.htm */ // Probably only works for Intel and AMD chips, and probably only for some of // them. @@ -174,6 +174,9 @@ micro_ops_warn(32, 32, 32); break; + /* not sectored, whatever that might mean */ + case 0x78: *L2c = (cache_t) { 1024, 4, 64 }; L2_found = True; break; + /* These are sectored, whatever that means */ case 0x79: *L2c = (cache_t) { 128, 8, 64 }; L2_found = True; break; case 0x7a: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break; |
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From: Nicholas N. <n.n...@gm...> - 2009-08-28 23:19:55
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On Sat, Aug 29, 2009 at 8:34 AM, <sv...@va...> wrote: > Author: sewardj > Date: 2009-08-28 23:34:09 +0100 (Fri, 28 Aug 2009) > New Revision: 10878 > > Log: > Add support for the L2 cache on Intel T4200. Presumably callgrind should get this change too. Nick |
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From: Julian S. <js...@ac...> - 2009-08-28 23:25:52
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On Saturday 29 August 2009 01:19:45 am Nicholas Nethercote wrote: > > Log: > > Add support for the L2 cache on Intel T4200. > > Presumably callgrind should get this change too. Yes it definitely should. I thought (had assumed) that Callgrind and Cachegrind share the same cache detection code. Is that not the case? J |
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From: Tom H. <to...@co...> - 2009-08-28 23:33:41
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On 29/08/09 00:25, Julian Seward wrote: > On Saturday 29 August 2009 01:19:45 am Nicholas Nethercote wrote: > >>> Log: >>> Add support for the L2 cache on Intel T4200. >> >> Presumably callgrind should get this change too. > > Yes it definitely should. I thought (had assumed) that Callgrind and > Cachegrind share the same cache detection code. Is that not the case? I believe they were separate but it looks like they were merged as callgrind is now pulling in the code from cachegrind. Tom -- Tom Hughes (to...@co...) http://www.compton.nu/ |
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From: Josef W. <Jos...@gm...> - 2009-09-07 15:32:44
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On Saturday 29 August 2009, Tom Hughes wrote: > On 29/08/09 00:25, Julian Seward wrote: > > On Saturday 29 August 2009 01:19:45 am Nicholas Nethercote wrote: > > > >>> Log: > >>> Add support for the L2 cache on Intel T4200. > >> > >> Presumably callgrind should get this change too. > > > > Yes it definitely should. I thought (had assumed) that Callgrind and > > Cachegrind share the same cache detection code. Is that not the case? > > I believe they were separate but it looks like they were merged as > callgrind is now pulling in the code from cachegrind. As far as I remember, Callgrind (since its merge) always pulled in the detection of cache parameters from Cachegrind, as this was nicely separated from the rest of the code. Just a remark about the comment... AFAIK, the term "sectored" means on Intel processors a simple kind of hardware prefetching, where memory is partitioned into "sectors" consisting of 2 adjacent memory blocks the size of a cache line. When one memory block of a sector is fetched into the cache because of a load instruction, the other memory block of the sector is prefetched. This is a very simple stream prefetching heuristic, both for upwards and downwards streams. This has the consequence that for code doing sequential load accesses, it looks like the cache has a line size of 128 byte (instead of the real 64 byte), also when looking at performance counters. Please correct me if I am wrong... Josef > > Tom > |
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From: Tom H. <to...@co...> - 2009-09-07 15:50:26
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On 07/09/09 16:31, Josef Weidendorfer wrote: > On Saturday 29 August 2009, Tom Hughes wrote: >> On 29/08/09 00:25, Julian Seward wrote: >>> On Saturday 29 August 2009 01:19:45 am Nicholas Nethercote wrote: >>> >>>>> Log: >>>>> Add support for the L2 cache on Intel T4200. >>>> >>>> Presumably callgrind should get this change too. >>> >>> Yes it definitely should. I thought (had assumed) that Callgrind and >>> Cachegrind share the same cache detection code. Is that not the case? >> >> I believe they were separate but it looks like they were merged as >> callgrind is now pulling in the code from cachegrind. > > As far as I remember, Callgrind (since its merge) always pulled in the detection > of cache parameters from Cachegrind, as this was nicely separated from the rest > of the code. I think I was mis-remembering - what I was thinking of was the fact that x86 and amd64 used to be more or less exact duplicates of each other in cachegrind but they have now been merged. Tom -- Tom Hughes (to...@co...) http://www.compton.nu/ |
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From: Nicholas N. <n.n...@gm...> - 2009-09-07 22:13:07
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On Tue, Sep 8, 2009 at 1:50 AM, Tom Hughes<to...@co...> wrote: >> >> As far as I remember, Callgrind (since its merge) always pulled in the detection >> of cache parameters from Cachegrind, as this was nicely separated from the rest >> of the code. > > I think I was mis-remembering - what I was thinking of was the fact that > x86 and amd64 used to be more or less exact duplicates of each > other in cachegrind but they have now been merged. You're both right. There's now a single file dealing with this stuff, cachegrind/cg-x86-amd64.c, which is used by both Cachegrind and Callgrind. Nick |