https://sourceware.org/cgit/valgrind/commit/?id=8436a7c61c07563bdc9fb1686c82821e74784dcf
commit 8436a7c61c07563bdc9fb1686c82821e74784dcf
Author: Florian Krohm <fl...@ei...>
Date: Sat Aug 2 13:14:31 2025 +0000
ARM specific changes for BZ 507033
Rework code to use Iop_ClzNat32 instead of the deprecated Iop_Clz32.
Iop_Clz32 --isel--> ARMun_CLZ --emit--> CLZ insn with CLZ(0) == 32
Hence, any workaround for a zero input value can be removed.
Part of fixing https://bugs.kde.org/show_bug.cgi?id=507033
Diff:
---
VEX/priv/guest_arm_toIR.c | 12 ++----------
VEX/priv/host_arm_isel.c | 9 +--------
memcheck/tests/vbit-test/irops.c | 4 ++--
3 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 2bedccd14d..673e876288 100644
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -17100,11 +17100,7 @@ DisResult disInstr_ARM_WRK (
IRTemp arg = newTemp(Ity_I32);
IRTemp res = newTemp(Ity_I32);
assign(arg, getIRegA(rM));
- assign(res, IRExpr_ITE(
- binop(Iop_CmpEQ32, mkexpr(arg), mkU32(0)),
- mkU32(32),
- unop(Iop_Clz32, mkexpr(arg))
- ));
+ assign(res, unop(Iop_ClzNat32, mkexpr(arg)));
putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
goto decode_success;
@@ -22730,11 +22726,7 @@ DisResult disInstr_THUMB_WRK (
IRTemp arg = newTemp(Ity_I32);
IRTemp res = newTemp(Ity_I32);
assign(arg, getIRegT(rM1));
- assign(res, IRExpr_ITE(
- binop(Iop_CmpEQ32, mkexpr(arg), mkU32(0)),
- mkU32(32),
- unop(Iop_Clz32, mkexpr(arg))
- ));
+ assign(res, unop(Iop_ClzNat32, mkexpr(arg)));
putIRegT(rD, mkexpr(res), condT);
DIP("clz r%u, r%u\n", rD, rM1);
goto decode_success;
diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c
index d19efe5c3e..4b76a6170a 100644
--- a/VEX/priv/host_arm_isel.c
+++ b/VEX/priv/host_arm_isel.c
@@ -1870,14 +1870,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
//zz addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, dst));
//zz return dst;
//zz }
-//zz case Iop_Ctz32: {
-//zz /* Count trailing zeroes, implemented by x86 'bsfl' */
-//zz HReg dst = newVRegI(env);
-//zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//zz addInstr(env, X86Instr_Bsfr32(True,src,dst));
-//zz return dst;
-//zz }
- case Iop_Clz32: {
+ case Iop_ClzNat32: {
/* Count leading zeroes; easy on ARM. */
HReg dst = newVRegI(env);
HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index fdea8919e4..2f0ea8a6af 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -109,11 +109,11 @@ static irop_t irops[] = {
{ DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts
{ DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert
{ DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts
- { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
+ { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
{ DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
{ DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
{ DEFOP(Iop_ClzNat64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts
- { DEFOP(Iop_ClzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
+ { DEFOP(Iop_ClzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 },
{ DEFOP(Iop_CtzNat64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
{ DEFOP(Iop_CtzNat32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 1, .mips32 =0, .mips64 = 0 },
{ DEFOP(Iop_PopCount64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 },
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